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PDP83TG720SWCSTQ1 Datasheet(PDF) 70 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 70 Page - Texas Instruments |
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70 / 199 page ![]() 7.6.2.14 MII_REG_1F Register (Address = 0x1F) [reset = 0x0] MII_REG_1F is shown in Table 7-37. Return to the Summary Table. Table 7-37. MII_REG_1F Register Field Descriptions Bit Field Type Reset Description 15 sw_global_reset R/WMC 1b0 Hardware reset - Reset digital + register file 14 digital_reset R/WMC 1b0 Soft reset - Reset only digital core 13 sor_debug_option R/W 1b0 Use sw_global_reset as RESET pin source 12-8 tp_sel_1_9_5 R/W 5b00000 Test port select[9:5] - Select module 7 standby_mode R/W 1b0 Reserved 6 standby_mode_ch_sel_B_ An R/W 1b0 Reserved 5 RESERVED R 1b0 Reserved 4-0 tp_sel_1_4_0 R/W 5b00000 Test port select[4:0] - Select signals within module DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 70 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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