HM530281R datasheet(9/47 Pages) HITACHI

9 / 47 page

Datasheet Title

CGR (clock gate for read) Input: CGR is an input signal that enables/disables incrementing of the

internal read address pointer.

When CGR is low, the read address pointer is incremented in

synchronization with the RCK read clock, and when high, incrementing is stopped. Therefore time axis

expansion can be easily implemented without stopping the read clock by using CGR.

WAS (write address set and jump) Input: WAS is an input signal that initiates write jump address input

when WRS is high and jumps to the previously input write jump address when WRS is low. The falling

edge of this input signal is detected, and either a write jump address input is initiated or a jump to the

previously input write jump address is executed on the first WCK cycle following the fall of WAS.

WAD (write jump address) Input: WAD is the input pin for the write jump address. The 14/15 bits of

the write jump address are read in sequentially from the high order bit, starting at the WCK cycle (when

WRS was high) in which WAS was set low.*2

RAS (read address set and jump) Input: RAS is an input signal that initiates read jump address input

when RRS is high and jumps to the previously input read jump address when RRS is low. The falling edge

of this input signal is detected, and either the read jump address input is initiated or the jump to the

previously input read jump address is executed on the first WCK cycle following the fall on RAS.

RAD (read jump address) Input: RAD is the input pin for the read jump address. The 14/15 bits of the

write jump address are read in sequentially from the high order bit, starting at the RCK cycle (when RRS

was high) in which RAS was set low.

HM530281R Datasheet(PDF) 9 Page - Hitachi Semiconductor