HM530281R datasheet(8/47 Pages) HITACHI

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Datasheet Title

Input and Output Pin Functions

IN0 to D IN7 (data input) Input:

The D

IN pins input 8 bits of data.

Data is input on the rising edge of the

cycle of WCK that follows a low level on both CGW and WE.

OUT0 to D OUT7 (data output) Output:

The D

OUT pins output 8 bits of data.

Data output is synchronized

with the RCK clock, and the access time is specified from the rising edge of the RCK cycle.

WCK (write clock) Input: WCK is the write clock input pin. The input of write data is synchronized

with this clock. Write data is input on the rising edge of the cycle of WCK that follows a low level on both

CGW and WE, and when CGW is low, the internal write address pointer is incremented at the same time.

Input of the write jump address is also synchronized with this clock. The 14 bits or 15 bits of the write

jump address are read in sequentially from the WCK cycle that set WAS low, irrespective of write data

acquisition.

RCK (read clock) Input: RCK is the read clock input pin. Read data is output in synchronization with

this clock when both CGR and OE are low, and when CGR is low, the internal read address pointer is

incremented at the same time. Input of the read jump address is also synchronized with this clock. The

read jump address is read in sequentially starting at the RCK cycle in which RAS was set low,

independently of read data output.

WRS (write address pointer reset) Input: WRS is a reset signal input that resets the write address

pointer to 0 when WAS and WLRS are high, resets to the head of the line currently being written when

WAS is high and WLRS is low, and jumps to the preset write jump address when WAS is low. *1 Only the

falling edge of this reset input is detected, and, on the first WCK cycle following that falling edge, a write

cycle to the set address is started immediately.

RRS (read address pointer reset) Input: RRS is a reset signal input that resets the read address pointer to

0 when RAS and RLRS are high, resets to the start of the line currently being read when RAS is high and

RLRS is low, and jumps to the read jump address when RAS is low.*1 Only the falling edge of this reset

input is detected, and, on the first RCK cycle following that falling edge, a read cycle at the set address is

started immediately.

WE (write enable) Input: WE is an input signal that controls the enabling/disabling of the data input pins.

When WE is low, input data is acquired on the WCK cycle, and when WE is high, data input is disabled

and the previous memory data is maintained. Note that the write address pointer is incremented by the

WCK write clock without regard for the level of WE.

OE (output enable) Input: OE is an input signal that enables/disables the data output pins. When OE is

low, data output is enabled, and when high, data output is disabled and the output pins go to the high

impedance state. Note that the read address pointer is incremented by the RCK read clock without regard

for the level of OE. Therefore, data can be jumped over during read simply by disabling output with OE.

CGW (clock gate for write) Input: CGW is an input signal that enables/disables incrementing of the

internal write address pointer.

When CGW is low, the write address pointer is incremented in

synchronization with the WCK write clock, and when high, incrementing is stopped. Therefore time axis

compression can be easily implemented without stopping the write clock by using CGW.

HM530281R Datasheet(PDF) 8 Page - Hitachi Semiconductor

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