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CS5501-BP Datasheet(PDF) 28 Page - Cirrus Logic |
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CS5501-BP Datasheet(HTML) 28 Page - Cirrus Logic |
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28 / 54 page ![]() CS5501 CS5503 28 DS31F4 to ensure that logic inputs are maintained at either VD+ ar DGND potential when SLEEP is low. Note that battery life could be shortened if the +5 V supply drops slowly during power-down. As the supply drops below the battery voltage but not yet below the logic threshold of the SLEEP pin, the battery will be supplying the CS5501/CS5503 at full power (typically 3 mA). Faster transitions at SLEEP can be triggered using a resistive divider or a simple resistor network to generate the SLEEP in- put from the +5 V supply. Output Loading Considerations To maximize performance of the CS5501/ CS5503, the output drive currents from the digital output lines should be minimized. Schematic & Layout Review Service CS5501 CS5503 28 DS31F5 |
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