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IMX7SCEC Datasheet(PDF) 90 Page - NXP Semiconductors |
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IMX7SCEC Datasheet(HTML) 90 Page - NXP Semiconductors |
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90 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 90 4.10.6 LCD controller (LCDIF) timing parameters Figure 60 shows the LCDIF timing and Table yy lists the timing parameters. Figure 60. LCD timing 4.10.7 Parallel CMOS sensor interface (CSI) timing parameters 4.10.7.1 Gated clock mode timing Figure 61 and Figure 62 shows the gated clock mode timings for CSI, and Table 67 describes the timing parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on CSI_VSYNC Table 66. LCD timing parameters ID Parameter Symbol Min Max Unit L1 LCD pixel clock frequency tCLK(LCD) - 150 MHz L2 LCD pixel clock high (falling edge capture) tCLKH(LCD) 3 - ns L3 LCD pixel clock low (rising edge capture) tCLKL(LCD) 3 - ns L4 LCD pixel clock high to data valid (falling edge capture) td(CLKH-DV) -1 1 ns L5 LCD pixel clock low to data valid (rising edge capture) td(CLKL-DV) -1 1 ns L6 LCD pixel clock high to control signals valid (falling edge capture) td(CLKH-CTRLV) -1 1 ns L7 LCD pixel clock low to control signals valid (rising edge capture) td(CLKL-CTRLV) -1 1 ns |
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