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IMX7SCEC Datasheet(PDF) 70 Page - NXP Semiconductors

No. de pieza IMX7SCEC
Descripción Electrónicos  i.MX 7Solo Family
PDF  152 Pages
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Fabricante Electrónico  NXP [NXP Semiconductors]
Página de inicio  http://www.nxp.com
Logo NXP - NXP Semiconductors

IMX7SCEC Datasheet(HTML) 70 Page - NXP Semiconductors

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Electrical characteristics
i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017
NXP Semiconductors
70
In EDO mode (Figure 36), NF16/NF17 are different from the definition in non-EDO mode (Figure 35).
They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical value for them
are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will
sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The
delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 7Dual
Application Processor Reference Manual [IMX7DRM]). The typical value of this control register is 0x8
at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value should
be made larger to compensate the board delay.
4.9.2
Source Synchronous mode AC timing (ONFI 2.x compatible)
Figure 38 to Figure 40 show the write and read timing of Source Synchronous mode.
Figure 38. Source Synchronous mode command and address timing diagram



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