IMX7SCEC datasheet(4/152 Pages) NXP

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IMX7SCEC Datasheet(PDF) 4 Page - NXP Semiconductors

4 / 152 page

i.MX 7Solo introduction

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

Figure 1 describes the part number nomenclature so that the users can identify the characteristics of the

specific part number.

Figure 1. Part number nomenclature—i.MX 7Solo family of processors

1.2

Features

The i.MX 7Solo family of processors is based on ARM Cortex-A7 MPCore™ Platform, which has the

following features:

•

ARM Cortex-A7 Core (with TrustZone® technology)

•The core includes:

— 32 KByte L1 Instruction Cache

— 32 KByte L1 Data Cache

— Private Timer and Watchdog

— NEON MPE (media processing engine) coprocessor

The ARM Cortex-A7 Core complex shares:

•

General interrupt controller (GIC) with 128 interrupt support

•

Global timer

•

Snoop control unit (SCU)

•

512 KB unified I/D L2 cache

•

Two master AXI bus interfaces output of L2 cache

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