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PSD813F2 Datasheet(PDF) 99 Page - STMicroelectronics

No. de pieza PSD813F2
Descripción Electrónicos  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PDF  110 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F2 Datasheet(HTML) 99 Page - STMicroelectronics

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 70. ISC Timing (3V devices)
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Table 71. Power-down Timing (5V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Table 72. Power-down Timing (3V devices)
Note: 1. tCLCL is the period of CLKIN (PD1).
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
tISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note 1)
12
10
9
MHz
tISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note 1)
40
45
51
ns
tISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note 1)
40
45
51
ns
tISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note 2)
22
2
MHz
tISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note 2)
240
240
240
ns
tISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note 2)
240
240
240
ns
tISCPSU
ISC Port Set Up Time
12
13
15
ns
tISCPH
ISC Port Hold Up Time
5
5
5
ns
tISCPCO
ISC Port Clock to Output
30
36
40
ns
tISCPZV
ISC Port High-Impedance to Valid Output
30
36
40
ns
tISCPVZ
ISC Port Valid Output to
High-Impedance
30
36
40
ns
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min
Max
Min
Max
Min
Max
tLVDV
ALE Access Time from Power-down
80
90
150
ns
tCLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1)
15 * tCLCL
1
µs
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
tLVDV
ALE Access Time from Power-down
145
150
200
ns
tCLWH
Maximum Delay from APD Enable to
Internal PDN Valid Signal
Using CLKIN
(PD1)
15 * tCLCL
1
µs



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