PSD813F2 datasheet(60/110 Pages) STMICROELECTRONICS

No. de pieza	PSD813F2

Descripción Electrónicos	Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

PDF	110 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

Logo

60 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

60/110

Port D – Functionality and Structure

Port D has three I/O pins. See Figure 30 and Fig-

ure 31., page 61. This port does not support Ad-

dress Out mode, and therefore no Control

perform one or more of the following functions:

■

MCU I/O Mode

■

CPLD Output – External Chip Select (ECS0-

ECS2)

■

CPLD Input – direct input to the CPLD, no

Input Macrocells (IMC)

■

Slew rate – pins can be set up for fast slew

rate

Port D pins can be configured in PSDsoft Express

as input pins for other dedicated functions:

■

Address Strobe (ALE/AS, PD0)

■

CLKIN (PD1) as input to the macrocells flip-

flops and APD counter

■

PSD Chip Select Input (CSI, PD2). Driving this

signal High disables the Flash memory, SRAM

and CSIOP.

Figure 30. Port D Structure

DATA OUT

REG.

ECS[ 2: 0]

READ MUX

CPLD - INPUT

DIR REG.

DATA IN

ENABLE PRODUCT

TERM (.OE)

OUTPUT

SELECT

OUTPUT

MUX

PORT D PIN

DATA OUT

AI02889

PSD813F2 Datasheet(PDF) 60 Page - STMicroelectronics

PSD813F2 Datasheet(HTML) 60 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL