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PSD813F2 Datasheet(PDF) 81 Page - STMicroelectronics

No. de pieza PSD813F2
Descripción Electrónicos  Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V
PDF  110 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F2 Datasheet(HTML) 81 Page - STMicroelectronics

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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Figure 41. Synchronous Clock Mode Timing – PLD
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
Symbol
Parameter
Conditions
-70
-90
-15
Fast
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Min
Max
Min
Max
Min
Max
fMAX
Maximum
Frequency
External
Feedback
1/(tS+tCO)
40.0
30.30
25.00
MHz
Maximum
Frequency
Internal
Feedback
(fCNT)
1/(tS+tCO–10)
66.6
43.48
31.25
MHz
Maximum
Frequency
Pipelined Data
1/(tCH+tCL)
83.3
50.00
35.71
MHz
tS
Input Setup
Time
12
15
20
+ 2
+ 10
ns
tH
Input Hold Time
0
0
0
ns
tCH
Clock High Time
Clock Input
6
10
15
ns
tCL
Clock Low Time
Clock Input
6
10
15
ns
tCO
Clock to Output
Delay
Clock Input
13
18
22
– 2
ns
tARD
CPLD Array
Delay
Any macrocell
11
16
22
+ 2
ns
tMIN
Minimum Clock
Period 2
tCH+tCL
12
20
30
ns
tCH
tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860



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