PSD813F2 datasheet(64/110 Pages) STMICROELECTRONICS

64 / 110 page

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

64/110

For Users of the HC11 (or compatible)

The HC11 turns off its E clock when it sleeps.

Therefore, if you are using an HC11 (or compati-

ble) in your design, and you wish to use the Pow-

er-down mode, you must not connect the E clock

to CLKIN (PD1). You should instead connect a

crystal oscillator to CLKIN (PD1). The crystal oscil-

lator frequency must be less than 15 times the fre-

quency of AS. The reason for this is that if the

frequency is greater than 15 times the frequency

of AS, the PSD keeps going into Power-down

mode.

Other Power Saving Options

The PSD offers other reduced power saving op-

tions that are independent of the Power-down

mode. Except for the SRAM Stand-by and PSD

Chip Select Input (CSI, PD2) features, they are en-

abled by setting bits in PMMR0 and PMMR2.

Figure 33. Enable Power-down Flow Chart

PLD Power Management

The power and speed of the PLDs are controlled

by the Turbo Bit (Bit 3) in PMMR0. By setting the

bit to '1,' the Turbo mode is off and the PLDs con-

sume the specified stand-by current when the in-

puts are not switching for an extended time of

70ns. The propagation delay time is increased by

10ns after the Turbo Bit is set to '1' (turned off)

when the inputs change at a composite frequency

of less than 15 MHz. When the Turbo Bit is reset

to '0' (turned on), the PLDs run at full power and

speed. The Turbo Bit affects the PLD’s DC power,

AC power, and propagation delay.

Blocking MCU control signals with the bits of

PMMR2 can further reduce PLD AC power con-

sumption.

SRAM Standby Mode (Battery Backup). The

PSD supports a battery backup mode in which the

contents of the SRAM are retained in the event of

a power loss. The SRAM has Voltage Stand-by

(VSTBY, PC2) that can be connected to an external

battery. When VCC becomes lower than VSTBY

then the PSD automatically connects to Voltage

Stand-by (VSTBY, PC2) as a power source to the

SRAM. The SRAM Standby Current (ISTBY) is typ-

ically 0.5µA. The SRAM data retention voltage is

2V minimum. The Battery-on Indicator (VBATON)

can be routed to PC4. This signal indicates when

the VCC has dropped below VSTBY.

Enable APD

Set PMMR0 Bit 1 = 1

PSD in Power

Down Mode

ALE/AS idle

for 15 CLKIN

clocks?

RESET

Yes

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bits 4 and 5

and PMMR2 bits 2 through 6.

AI02892

PSD813F2 Datasheet(PDF) 64 Page - STMicroelectronics

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