FDMF2011 datasheet(23/31 Pages) ONSEMI

23 / 31 page

www.fairchildsemi.com

FDMF2011 Rev.1.0

Functional Description

The FDMF2011 is a non-inverting 100V half-

bridge Smart Power Stage (SPS) module. The

module packages a driver IC die along with

pair of equally sized (matched RDSON) 100V

PowerTrench

N-Channel

MOSFETs

(Standard gate thresholds refer to Table 5).

The FDMF2011 module provides separate

power input pins; the power stage input (VIN)

and the gate driver input (VDD). The power

stage input (VIN) accepts a wide operating

from 3V to 80V, while the gate driver input

(VDD) requires 10V to 20V. The module

accepts TTL compatible inputs (HI/LI) along

with anti-cross conduction circuitry to protect

against over-lapping PWM (HI/LI) pulses. The

module (driver IC) also implements UVLO

circuitry in both the VDD-VSS and BOOT-PH

power domains.

Power-Up and UVLO Operation

UVLO circuits are implemented in both the

VDD-VSS and HB-PH power domains. During

power-up, the VDD-VSS UVLO circuit forces

HO and LO low until the VDD supply voltage

exceeds the UVLO rising threshold (9.4V typ.).

The module (driver IC) will begin responding

to PWM pulses once VDD exceeds the UVLO

threshold. The UVLO circuit does contain

hysteresis (~0.6V) to prevent

noise from

interfering with normal operation. An additional

UVLO circuit is implemented on the HB-PH

pins which will hold HO low until HB-PH >

(9.4V

typ.).

The

HB-PH

UVLO

also

incorporates hysteresis (~0.6V).

VDD

UVLO

BOOT

UVLO

Driver State

Disabled (GH, GL=0)

GL follows PWM , GH=0)

Enabled (GH/GL follow PWM)

Table 6. UVLO Truth Table

Figure 62. Min/Max UVLO thresholds

PWM Input Stage

The FDMF2011 incorporates a PWM input

gate drive design, where the low side drive

output (LO) and high side drive output (HO)

are

controlled

through

independent

PWM

inputs (LI and HI, respectively).

The module (driver IC) can be used with TTL

compatible input signals. The input signals

can also be driven with voltage levels that are

lower than the VDD supply level. The VDD

supply

level

does

NOT

affect

the

input

threshold levels (VIH and VIL).

Figure 63. PWM threshold definitions

- VIH = PWM trip level to flip state from LOW to

HIGH.

- VIL = PWM trip level to flip state from HIGH to

LOW.

FDMF2011 Datasheet(PDF) 23 Page - ON Semiconductor

FDMF2011 Datasheet(HTML) 23 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Descarga

Enlace URL