CS53L30 datasheet(39/67 Pages) CIRRUS

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DS992F2

CS53L30

5.2 Power-Up Sequence

The CS53L30 includes a synchronization protocol that can be used to minimize channel-to-channel phase mismatch

across multiple CS53L30s in a system, as long as the phase mismatch is not of the Class 1 type (i.e., deterministic, time

invariant). An external phase calibration is necessary to nullify deterministic, time-invariant phase, which is beyond the

scope of this document. The power-up sequence in Section 5.2 is for applications without critical phase criteria, but can

be modified to minimize the other three classes of phase mismatch. First, ensure that the SYNC pins are connected as

shown in Fig. 5-1, then follow the power-up sequence of Ex. 5-1 with the following modification: Set SYNC_EN in Step 6.1.

Follow the rest of the power-up sequence as described in Section 5.2.

The phase-mismatch specifications in Table 3-5 are guaranteed only with MCLK = 19.2 MHz, the sample rate set to

16 kHz, with an 8-kHz fullscale tone as input. Phase mismatch uncertainty and MCLK period are positively correlated.

5.1.2

Gain-Calibration Considerations

The CS53L30 has a tightly controlled interchannel gain mismatch specification and should meet the requirements of most

multichannel applications. The system designer must consider that, from channel to channel and from device to device,

variations exist due to external-component manufacturing tolerances and CS53L30 process variations. These gain

variations should be nullified for optimal operation. The calibration procedure is very application specific and is left to the

system designer. Any calibration should take the synchronous SRC gain versus sample-rate data in Table 4-4 into

consideration. This data implies that any change in sample rate or in MCLK that is subsequent to calibration may require

a recalibration with the new conditions or at least a scale factor for best results.

5.2 Power-Up Sequence

Ex. 5-1 is a procedure for initiating serial capture of audio data via TDM in Master Mode with a 19.2-MHz MCLK and

16-kHz LRCK.

Example 5-1. Power-Up Sequence

STEP TASK

1 Assert reset by driving the RESET pin low.

2 Apply power first to VP and then to VA.

3 Apply a supported MCLK signal.

4 Deassert reset by driving the RESET pin high.

5 Write the following register

to power down the device.

VALUE

DESCRIPTION

Power Control, Address 0x06

0x50

PDN_ULP

PDN_LP

DISCHARGE_FILT+

THMS_PDN†

Reserved

0000

Ultralow power down is not enabled.

Power down is enabled.

FILT+ pin is not clamped to ground.

Thermal sense is powered down.

—

6 Write the following registers to configure MCLK and serial port settings.

STEP TASK

VALUE

DESCRIPTION

6.1 Configure MCLK.

MCLK Control, Address 0x07

0x08

MCLK_DIS

MCLK_INT_SCALE†

DMIC_DRIVE†

Reserved

MCLK_DIV[1:0]

SYNC_EN†

Reserved

Internal MCLK fanout is enabled.

Automatic MCLK scaling is disabled.

DMIC clock output drive strength is normal.

—

MCLKint = MCLKext/3.

Multichip synchronization is disabled.

—

6.2 Enable 19.2-MHz

MCLK, set internal FS

ratio.

Internal Sample Rate Control, Address 0x08

0x1D

Reserved

INTERNAL_FS_RATIO

Reserved

MCLK_19MHZ_EN

000

110

—

FSint = MCLKint/128.

—

MCLK is19.2 MHz.

6.3 Configure serial port. ASP Configuration Control, Address 0x0C

0x85

ASP_M/S

Reserved

ASP_SCLK_INV†

ASP_RATE[3:0]

0101

Serial port is master.

—

ASP_SCLK polarity is not inverted.

FSext is 16 kHz.

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