Wide Input Voltage Range, High-Efficiency,

Fault-Tolerant LED Driver

A8519 and

A8519-1

5

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

PINOUT DIAGRAMS

Terminal List Table

Pin Number

Name

Function

LP

ET

1

18

COMP

Output of the error amplifier and compensation node. Connect an Rz-Cz-Cp network from this pin to GND

for control loop compensation.

2

19,20,21

PGND

Power ground for internal N-channel MOSFET switching device. Connect to PCB ground plane.

3

22

OVP

Overvoltage protection. Connect external resistor from VOUT to this pin to adjust the overvoltage protection

level.

4

23

VOUT

Connect directly to boost output voltage.

5

25,26

SW

The drain of the internal N-channel MOSFET switching device of the boost converter.

6

27

GATE

Output gate driver pin for external P-channel MOSFET control.

7

28

VSENSE

Connect this pin to the negative sense side of the current sense resistor Rsc. The threshold voltage is

8

1

VIN

Input power to the IC as well as the positive input used for current sense resistor.

9

3

FAULT

The pin is an open-drain type configuration that will be pulled low when a fault occurs. Connect a 100 kW

resistor between this pin and desired logic level voltage.

10

4

CLKOUT

Logic output representing the switching frequency of internal boost oscillator. This allows other converters to

be synchronized to the same frequency (with the same frequency dithering, if applicable)

11

5

VDD

Output of internal LDO (bias regulator). Connect a 1 μF decoupling capacitor between this pin and GND.

12

6

APWM

current.

13

7

PWM

Enables the IC when this pin is pulled high. Also serves to control the LED intensity by using pulse-width

modulation. Typical PWM dimming frequency is in the range of 100 to 400 Hz.

14

8

FSET

dithering superimposed). It can also be used to synchronize two or more converters in the system to an

external frequency between 260 kHz and 2.3 MHz (dithering is disabled in this case).

15

9

ISET

16

10,11

AGND

LED current ground. Connect to PCB ground plane.

17,18,

19,20

13,14,

15,16

LED 1-4

LED current sinks #1 to 4. Connect the cathode of each LED string to associated pin. Unused LED pin must

be terminated to GND through a 3.09 kΩ resistor.

–

2,12,

17,24

NC

No connect. Leave open or connect to GND.

–

–

PAD

Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the

ground plane(s) of the PCB with at least 8 vias, directly in the pad.

1

COMP

LED4

2

PGND

LED3

3

OVP

LED2

4

VOUT

LED1

5

SW

AGND

6

GATE

ISET

7

VSENSE

FSET

8

VIN

PWM

9

FAULT

APWM

10

CLKOUT

VDD

PAD

11

12

13

14

15

16

17

18

19

20

2

VIN

3

FAULT

4

CLKOUT

5

VDD

6

APWM

7

PWM

15

LED3

16

LED4

17

NC

NC

18

COMP

19

PGND

20

PGND

21

PGND

1

28-Pin QFN with Exposed Thermal Pad (suffix ET)

20-Pin TSSOP with Exposed Thermal Pad (suffix LP)