1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC − No internal connection

VDD

IN

3V3

AGND

CLF

ILIM

NC

PVDD

PVDD

OUT

OUT

PGND

PGND

CS

UCD7100

www.ti.com

SLUS651D – MARCH 2005 – REVISED OCTOBER 2014

5 Description (continued)

For fast switching speeds, the UCD7100 output stage uses the TrueDrive™ output architecture, which delivers

rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. It

also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller.

The UCD7000 driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.

UCD7100 is offered in aPowerPAD™ HTSSOP-14.

6 Pin Configuration and Functions

PWP

14 PINS

Top View

Pin Functions

UCD7100

PIN

I/O

FUNCTION

HTSSOP

DFN-14

NAME

-14 PIN #

PIN #

Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to

1

1

VDD

I

15 V. Bypass the pin with at least 4.7 µF of capacitance.

The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up

2

2

IN

I

to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry

from any external noise.

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA

3

3

3V3

O

of current. Place 0.22-µF of ceramic capacitance from the pin to ground.

4

4

AGND

-

Analog ground return.

Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output

5

5

CLF

O

of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is

latched high until the UCD7K device receives the next rising edge on the IN pin.

Current limit threshold set pin. The current limit threshold can be set to any value between

6

6

ILIM

I

0.25 V and 1.0 V.

7

7

NC

-

No Connection.

Current sense pin. Fast current limit comparator connected to the CS pin is used to protect

8

8

CS

I

the power stage by implementing cycle-by-cycle current limiting.

Power ground return. Connect the two PGNDs together. These ground pins should be

9

9

PGND

-

connected very closely to the source of the power MOSFET.

Power ground return. Connect the two PGNDs together. These ground pins should be

10

10

PGND

-

connected very closely to the source of the power MOSFET.

11

11

OUT

O

The high-current TrueDrive™ driver output. Connect the two OUT pins together.

12

12

OUT

O

The high-current TrueDrive™ driver output. Connect the two OUT pins together.

Supply pin provides power for the output drivers. It is not connected internally to the VDD

13

13

PVDD

I

supply rail. Connect the two PVDD pins together.

Supply pin provides power for the output drivers. It is not connected internally to the VDD

14

14

PVDD

I

supply rail. Connect the two PVDD pins together.

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