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TNETV6446AINZWT Datasheet(PDF) 146 Page - Texas Instruments

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No. de pieza TNETV6446AINZWT
Descripción Electrónicos  Digital Media System-on-Chip
PDF  227 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV6446AINZWT Datasheet(HTML) 146 Page - Texas Instruments

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DMARQ
tDVH
tENV
DSTROBE (IORDY) (A)
STOP (DIOW) (A)
HDMARDY (DIOR) (A)
DD[15:0]
DA[2:0],
ATA_CS0,
ATA_CS1
tFS
tENV
tZFS
tDZFS
tDVS
tZAD
tZAD
tFS
tUI
tACK
tACK
tZIORDY
tAZ
tACK
DMACK
t2CYC
tDH
tDS
tDH
tDS
tDH
DSTROBE
(IORDY)
DD[15:0]
tCYC(A)
tCYC(A)
DMARQ
tRP
DSTROBE
(IORDY)
STOP (DIOW)
HDMARDY
(DIOR)
DD[15:0]
DMACK
tRFS
TMS320DM6446
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
www.ti.com
A.
The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-28. ATA/CF Initiating an Ultra DMA Data-In Burst Timing
A.
While DSTROBE (IORDY) timing is tCYC at the device, it may be different at the host due to propagation delay
differences on the cable.
Figure 6-29. ATA/CF Sustained Ultra DMA Data-In Data Transfer Timing
Figure 6-30. ATA/CF Host Pausing an Ultra DMA Data-In Burst Timing
146
Peripheral and Electrical Specifications
Copyright © 2005–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM6446



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