TNETV6446AINZWT datasheet(144/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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6.11.2.3 ATA/CF Ultra DMA Timing

Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing(1) (2)

(see Figure 6-28 through Figure 6-37)

A-513,

-594,

NO.

MODE

UNIT

-810

MIN

MAX

f(SYSCLK5)

Operating frequency, SYSCLK5

0-4

MHz

240

160

t2CYCTYP

Typical sustained average two cycle time

120

tCYC

Cycle time, Strobe edge to Strobe edge

0-4

(UDMASTB + 1)P

Two cycle time, rising to rising edge or falling to

t2CYC

0-4

2(UDMASTB + 1)P

falling edge

tDS

Data setup, data valid before STROBE edge

2-3

tDH

Data hold, data valid after STROBE edge

0-4

Data valid INPUT setup time, data valid before

STROBE

tDVS

6.7

Data valid OUTPUT setup time, data valid before

0-4

(UDMASTB)P - 3.1

STROBE

Data valid INPUT hold time, data valid after

0-4

6.2

STROBE

tDVH

Data valid OUTPUT hold time, data valid after

0-4

1P - 2

STROBE

CRC word valid setup time at host, CRC valid

tCVS

0-4

(UDMASTB)P

before DMACK negation

CRC word valid hold time at sender, CRC valid

tCVH

0-4

after DMACK negation

Time from STROBE output released-to-driving

tZFS

0-4

until the first transition of critical timing

Time from data output released-to-driving until

tDZFS

the first transition of critical timing

6.7

(1)

P = SYSCLK5 period, in ns, for ATA. For example, when running the DSP CPU at 594 MHz, use P = 10.1 ns. For example, when

running the DSP CPU at 810 MHz, use P = 7.4 ns.

(2)

UDMASTB equals the value programmed in the UDMSTBxP bit field in the UDMASTB register. UDMATRP equals the value

programmed in the UDMTRPxP bit field in the UDMATRP register. TENV equals the value programmed in the UDMATNVxP bit field in

the UDMATENV register. For more detailed information, see the TMS320DM644x DMSoC ATA Controller User's Guide (literature

number SPRUE21).

144

Peripheral and Electrical Specifications

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