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TNETV6446AINZWT Datasheet(PDF) 145 Page - Texas Instruments

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No. de pieza TNETV6446AINZWT
Descripción Electrónicos  Digital Media System-on-Chip
PDF  227 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
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TNETV6446AINZWT Datasheet(HTML) 145 Page - Texas Instruments

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TMS320DM6446
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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
Table 6-41. Timings for ATA/CF Module — Ultra DMA AC Timing
(see Figure 6-28 through Figure 6-37) (continued)
A-513,
-594,
NO.
MODE
UNIT
-810
MIN
MAX
0
230
ns
1
200
ns
14
tFS
First STROBE time
2
170
ns
3
130
ns
4
120
ns
15
tLI
Limited interlock time
0-4
0
150
ns
16
tMLI
Interlock time with minimum
0-4
20
ns
17
tUI
Unlimited interlock time
0-4
0
ns
Maximum time allowed for output drivers to
18
tAZ
0-4
10
ns
release
19
tZAH
Minimum delay time required for output
0-4
20
ns
Minimum delay time for driver to assert or negate
20
tZAD
0-4
0
ns
(from released)
Envelope time, DMACK to STOP and DMACK to
21
tENV
HDMARDY during in-burst initiation and from
0-4
(TENV + 1)P - 0.5
(TENV + 1)P + 1.4
ns
DMACK to STOP during data out burst initiation
0
75
ns
22
tRFS
Ready-to-final-STROBE time
1
70
ns
2-4
60
ns
Ready to pause time, (HDMARDY (DIOR) to
0-4
(UDMATRP + 1)P - 0.8
ns
STOP (DIOW))
0
160
ns
23
tRP
Ready to pause time, (DDMARDY (IORDY) to
1
125
ns
DMARQ)
2-4
100
ns
24
tIORDYZ
Maximum time before releasing IORDY
0-4
20
ns
25
tZIORDY
Minimum time before driving IORDY
0-4
0
ns
Setup and hold time for DMACK (before
26
tACK
0-4
20
ns
assertion or negation)
STROBE edge to negation of DMARQ or
27
tSS
assertion of STOP (when sender terminates a
0-4
50
ns
burst)
Copyright © 2005–2010, Texas Instruments Incorporated
Peripheral and Electrical Specifications
145
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Product Folder Link(s): TMS320DM6446



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