TNETV6446AINZWT datasheet(206/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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Table 6-90. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

01C8 0130

RX4FLOWTHRESH

Receive Channel 4 Flow Control Threshold Register

01C8 0134

RX5FLOWTHRESH

Receive Channel 5 Flow Control Threshold Register

01C8 0138

RX6FLOWTHRESH

Receive Channel 6 Flow Control Threshold Register

01C8 013C

RX7FLOWTHRESH

Receive Channel 7 Flow Control Threshold Register

01C8 0140

RX0FREEBUFFER

Receive Channel 0 Free Buffer Count Register

01C8 0144

RX1FREEBUFFER

Receive Channel 1 Free Buffer Count Register

01C8 0148

RX2FREEBUFFER

Receive Channel 2 Free Buffer Count Register

01C8 014C

RX3FREEBUFFER

Receive Channel 3 Free Buffer Count Register

01C8 0150

RX4FREEBUFFER

Receive Channel 4 Free Buffer Count Register

01C8 0154

RX5FREEBUFFER

Receive Channel 5 Free Buffer Count Register

01C8 0158

RX6FREEBUFFER

Receive Channel 6 Free Buffer Count Register

01C8 015C

RX7FREEBUFFER

Receive Channel 7 Free Buffer Count Register

01C8 0160

MACCONTROL

MAC Control Register

01C8 0164

MACSTATUS

MAC Status Register

01C8 0168

EMCONTROL

Emulation Control Register

01C8 016C

FIFOCONTROL

FIFO Control Register (Transmit and Receive)

01C8 0170

MACCONFIG

MAC Configuration Register

01C8 0174

SOFTRESET

Soft Reset Register

01C8 01D0

MACSRCADDRLO

MAC Source Address Low Bytes Register (Lower 16-bits)

01C8 01D4

MACSRCADDRHI

MAC Source Address High Bytes Register (Upper 32-bits)

01C8 01D8

MACHASH1

MAC Hash Address Register 1

01C8 01DC

MACHASH2

MAC Hash Address Register 2

01C8 01E0

BOFFTEST

Back Off Test Register

01C8 01E4

TPACETEST

Transmit Pacing Algorithm Test Register

01C8 01E8

RXPAUSE

Receive Pause Timer Register

01C8 01EC

TXPAUSE

Transmit Pause Timer Register

01C8 0200 - 01C8 02FC

(see Table 6-91)

EMAC Statistics Registers

01C8 0500

MACADDRLO

MAC Address Low Bytes Register

01C8 0504

MACADDRHI

MAC Address High Bytes Register

01C8 0508

MACINDEX

MAC Index Register

01C8 0600

TX0HDP

Transmit Channel 0 DMA Head Descriptor Pointer Register

01C8 0604

TX1HDP

Transmit Channel 1 DMA Head Descriptor Pointer Register

01C8 0608

TX2HDP

Transmit Channel 2 DMA Head Descriptor Pointer Register

01C8 060C

TX3HDP

Transmit Channel 3 DMA Head Descriptor Pointer Register

01C8 0610

TX4HDP

Transmit Channel 4 DMA Head Descriptor Pointer Register

01C8 0614

TX5HDP

Transmit Channel 5 DMA Head Descriptor Pointer Register

01C8 0618

TX6HDP

Transmit Channel 6 DMA Head Descriptor Pointer Register

01C8 061C

TX7HDP

Transmit Channel 7 DMA Head Descriptor Pointer Register

01C8 0620

RX0HDP

Receive Channel 0 DMA Head Descriptor Pointer Register

01C8 0624

RX1HDP

Receive Channel 1 DMA Head Descriptor Pointer Register

01C8 0628

RX2HDP

Receive Channel 2 DMA Head Descriptor Pointer Register

01C8 062C

RX3HDP

Receive Channel 3 DMA Head Descriptor Pointer Register

01C8 0630

RX4HDP

Receive Channel 4 DMA Head Descriptor Pointer Register

01C8 0634

RX5HDP

Receive Channel 5 DMA Head Descriptor Pointer Register

01C8 0638

RX6HDP

Receive Channel 6 DMA Head Descriptor Pointer Register

01C8 063C

RX7HDP

Receive Channel 7 DMA Head Descriptor Pointer Register

Transmit Channel 0 Completion Pointer (Interrupt Acknowledge)

01C8 0640

TX0CP

206

Peripheral and Electrical Specifications

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