TNETV6446AINZWT datasheet(205/227 Pages) TI1

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TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

6.20 Ethernet Media Access Controller (EMAC)

The Ethernet Media Access Controller (EMAC) provides an efficient interface between DM6446 and the

network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and

100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)

support.

The EMAC controls the flow of packet data from the DM6446 device to the PHY. The MDIO module

controls PHY configuration and status monitoring.

Both the EMAC and the MDIO modules interface to the DM6446 device through a custom interface that

allows efficient data transmission and reception. This custom interface is referred to as the EMAC control

module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used to

multiplex and control interrupts.

For more detailed information on the EMAC peripheral, see the TMS320DM644x DMSoC Ethernet Media

Access Controller (EMAC)/Management Data Input/Output (MDIO) Module User's Guide (literature

number SPRUE24). For a list of supported registers and register fields, see Table 6-90 [Ethernet MAC

(EMAC) Control Registers] and Table 6-91 [EMAC Statistics Registers] in this data manual.

6.20.1

EMAC Peripheral Register Description(s)

Table 6-90. Ethernet MAC (EMAC) Control Registers

HEX ADDRESS RANGE

ACRONYM

01C8 0000

TXIDVER

Transmit Identification and Version Register

01C8 0004

TXCONTROL

Transmit Control Register

01C8 0008

TXTEARDOWN

Transmit Teardown Register

01C8 0010

RXIDVER

Receive Identification and Version Register

01C8 0014

RXCONTROL

Receive Control Register

01C8 0018

RXTEARDOWN

Receive Teardown Register

01C8 0080

TXINTSTATRAW

Transmit Interrupt Status (Unmasked) Register

01C8 0084

TXINTSTATMASKED

Transmit Interrupt Status (Masked) Register

01C8 0088

TXINTMASKSET

Transmit Interrupt Mask Set Register

01C8 008C

TXINTMASKCLEAR

Transmit Interrupt Mask Clear Register

01C8 0090

MACINVECTOR

MAC Input Vector Register

01C8 00A0

RXINTSTATRAW

Receive Interrupt Status (Unmasked) Register

01C8 00A4

RXINTSTATMASKED

Receive Interrupt Status (Masked) Register

01C8 00A8

RXINTMASKSET

Receive Interrupt Mask Set Register

01C8 00AC

RXINTMASKCLEAR

Receive Interrupt Mask Clear Register

01C8 00B0

MACINTSTATRAW

MAC Interrupt Status (Unmasked) Register

01C8 00B4

MACINTSTATMASKED

MAC Interrupt Status (Masked) Register

01C8 00B8

MACINTMASKSET

MAC Interrupt Mask Set Register

01C8 00BC

MACINTMASKCLEAR

MAC Interrupt Mask Clear Register

01C8 0100

RXMBPENABLE

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

01C8 0104

RXUNICASTSET

Receive Unicast Enable Set Register

01C8 0108

RXUNICASTCLEAR

Receive Unicast Clear Register

01C8 010C

RXMAXLEN

Receive Maximum Length Register

01C8 0110

RXBUFFEROFFSET

Receive Buffer Offset Register

01C8 0114

RXFILTERLOWTHRESH

Receive Filter Low Priority Frame Threshold Register

01C8 0120

RX0FLOWTHRESH

Receive Channel 0 Flow Control Threshold Register

01C8 0124

RX1FLOWTHRESH

Receive Channel 1 Flow Control Threshold Register

01C8 0128

RX2FLOWTHRESH

Receive Channel 2 Flow Control Threshold Register

01C8 012C

RX3FLOWTHRESH

Receive Channel 3 Flow Control Threshold Register

Peripheral and Electrical Specifications

205

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