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TNETV1644ZDU6 Datasheet(PDF) 151 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 151 Page - Texas Instruments |
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151 / 306 page  TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 Table 3-57. EMIFA/VPSS Sub-Block 1 Pin-By-Pin Mux Control MULTIPLEXED FUNCTIONS SIGNAL VPBE VPBE EMIFA GPIO NAME EXTRA FUNCTIONS FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT HSYNC/EM_CS5/GP[33] HSYNC CS5SEL = 2 – – EM_CS5 CS5SEL = 1 GP[33] CS5SEL = 0 VSYNC/EM_CS4/GP[32] VSYNC CS4SEL = 2 – – EM_CS4 CS4SEL = 1 GP[32] CS4SEL = 0 VPBECLK/GP[30] VPBECLK VPBECKEN = 1 – – – – GP[30] VPBECKEN = 0 VCLK/GP[31] VCLK VENCSEL = 1/2 – – – – GP[31] VENCSEL = 0 YOUT7/GP[29] YOUT7 – – – – GP[29] YOUT6/GP[28] YOUT6 – – – – GP[28] YOUT5/GP[27] YOUT5 – – – – GP[27] YOUT4/GP[26]/(FASTBOOT) YOUT4 – – – – GP[26] YOUT3/GP[25]/(BOOTMODE3) YOUT3 – – – – GP[25] YOUT2/GP[24]/(BOOTMODE2) YOUT2 – – – – GP[24] YOUT1/GP[23]/(BOOTMODE1) YOUT1 – – – – GP[23] YOUT0/GP[22]/(BOOTMODE0) YOUT0 – – – – GP[22] COUT7/EM_D[7]/GP[21] COUT7 VENCSEL = 2, – – EM_D[7] VENCSEL = GP[21] VENCSEL = AEM = 0/3/4 0/1, 0/1, COUT6/EM_D[6]/GP[20] COUT6 – – EM_D[6] GP[20] AEM = 1/5 AEM = 0/3/4 COUT5/EM_D[5]/GP[19] COUT5 – – EM_D[5] GP[19] COUT4/EM_D[4]/GP[18] COUT4 – – EM_D[4] GP[18] COUT3/EM_D[3]/GP[17] COUT3 – – EM_D[3] GP[17] COUT2/EM_D[2]/GP[16] COUT2 – – EM_D[2] GP[16] COUT1/EM_D[1]/GP[15] COUT1 – – EM_D[1] GP[15] COUT0/EM_D[0]/GP[14] COUT0 – – EM_D[0] GP[14] LCD_OE/EM_CS3/GP[13] LCD_OE CS3SEL = 2 – – EM_CS3 CS3SEL = 1 GP[13] CS3SEL = 0 G0/EM_CS2/GP[12] G0 – – EM_CS2 GP[12] G1/EM_A[1]/(ALE)/ RGBSEL = RGBSEL = G1 – – EM_A[1]/(ALE) GP[9] GP[9]/(AEAW1/PLLMS1) 0/1 (1), 0/1/2/3, AEM = 1/3/4/5 AEM = 0 B1/EM_A[2]/(CLE)/GP[8]/ B1 – – EM_A[2]/(CLE) GP[8] (AEAW0/PLLMS0) RGBSEL = 4, LCD_FIELD RGBSEL = EM_A[3] GP[11] RGBSEL = AEM = 0 B0/LCD_FIELD/EM_A[3]/GP[11 B0 1/3 (1), 0/2 (1), ] AEM = 0/4/5 AEM = 0/4/5 R0/EM_A[4]/GP[10]/ RGBSEL = R0 – – EM_A[4] GP[10] RGBSEL = 0, (AEAW2/PLLMS2) 0/1/2/3 (1), AEM = 1/3 AEM = 0/4/5 R1/EM_A[0]/GP[7]/(AEM2) R1 – – EM_A[0] GP[7] R2/EM_BA[0]/GP[6]/(AEM1) R2 RGBSEL = – – EM_BA[0] GP[6] RGBSEL = 0/1, 2/3/4, AEM = 0/4/5 B2/EM_BA[1]/GP[5]/(AEM0) B2 – – EM_BA[1] GP[5] AEM = 0 (1) Valid RGBSEL settings depend on AEM mode: • RGBSEL = 0 is valid for AEM[2:0] = 0/1/3/4/5 • RGBSEL = 1 is only valid if AEM[2:0] = 0/4/5 • RGBSEL = 2/3/4 is only valid if AEM[2:0] = 0 Table 3-58. EMIFA/VPSS Sub-Block 3 Pin-By-Pin Mux Control MULTIPLEXED FUNCTIONS SIGNAL NAME EMIFA PCI GPIO FUNCTION SELECT FUNCTION SELECT FUNCTION SELECT EM_A[12]/PCBE3/GP[89] EM_A[12] PCBE3 GP[89] EM_A[11]/AD24/GP[90] EM_A[11] AD24 GP[90] EM_A[10]/AD23/GP[91] EM_A[10] AD23 GP[91] EM_A[9]/PIDSEL/GP[92] EM_A[9] PIDSEL GP[92] PCIEN = 0, PCIEN = 1, PCIEN = 0, AEM = 1/3 AEM = 0/5 AEM = 0/4/5 EM_A[8]/AD21/GP[93] EM_A[8] AD21 GP[93] EM_A[7]/AD22/GP[94] EM_A[7] AD22 GP[94] EM_A[6]/AD20/GP[95] EM_A[6] AD20 GP[95] EM_A[5]/AD19/GP[96] EM_A[5] AD19 GP[96] Submit Documentation Feedback Device Configurations 151 |
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