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3.8 Device Initialization Sequence After Reset

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

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Software should follow this initialization sequence after coming out of device reset.

1. Complete the boot sequence as needed. For more details on the boot sequence, see the Using the

TMS320DM643x Bootloader Application Report (literature number SPRAAG0).

2. If the device is not already at the desired operating frequency, program the PLL Controllers (PLLC1

and PLLC2) to configure the device frequency. For details on how to program the PLLC, see the

TMS320DM643x DMP DSP Subsystem Reference Guide (literature number SPRU978).

3. Program PINMUX0 and PINMUX1 registers to select device pin functions. For more details on

programming the PINMUX0 and PINMUX1 registers to select device pin functions, see Section 3.7,

Multiplexed Pin Configurations.

Note: If EMAC operation is desired, the EMAC must be placed in reset before programming

PINMUX1.HOSTBK to select EMAC pins.

4. Program the VDD3P3V_PWDN register to power up the necessary I/O pins. For more details on

programming the VDD3P3V_PWDN register, see Section 3.2, Power Considerations.

5. As needed by the application, program the following System Module registers when there are no active

transactions on the respective peripherals:

HPICTL (Section 3.6.2.1, HPI Control Register): applicable for HPI only if a different host burst

write timeout value from default is desired.

TIMERCTL (Section 3.6.2.2, Timer Control Register): applicable for Timer0 and Watchdog Timer2

only.

EDMATCCFG (Section 3.6.2.3, EDMA TC Configuration Register): applicable for EDMA only. The

recommendation is to leave the EDMATCCFG register at its default.

VPSS_CLKCTL (Section 3.3.2, VPSS Clocks): applicable for VPSS only.

6. Program the Power and Sleep Controller (PSC) to enable the desired peripherals. For details on how

to program the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature

number SPRU978).

7. Program the Switched Central Resource (SCR) bus priorities for the master peripherals

(Section 3.6.1). This must be configured when there are no active transactions on the respective

peripherals:

Program the MSTPRI0 and MSTPRI1 registers in the System Module. These registers can be

programmed before or after the respective peripheral is enabled by the PSC in step 6.

Program the EDMACC QUEPRI register, the C64x+ MDMAARBE.PRI field, and the VPSS PCR

PSC in step 6.

8. Configure the C64x+ Megamodule and the peripherals.

For details on C64x+ Megamodule configuration, see the TMS320C64x+ DSP Megamodule

Reference Guide (literature number SPRU871).

Special considerations: Bootloader disables C64x+ cache—For all boot modes that default to

DSPBOOTADDR = 0x0010 0000 (i.e., all boot modes except the EMIFA ROM Direct Boot,

BOOTMODE[3:0] = 0100, FASTBOOT = 0), the bootloader code disables all C64x+ cache (L2,

L1P, and L1D) so that upon exit from the bootloader code, all C64x+ memories are configured as

all RAM (L2CFG.L2MODE = 0h, L1PCFG.L1PMODE = 0h, and L1DCFG.L1DMODE = 0h). If cache

use is required, the application code must explicitly enable the cache. For more information on boot

modes, see Section 3.4.1, Boot Modes. For more information on the bootloader, see the Using the

TMS320DM643x Bootloader Application Report (literature number SPRAAG0).

Device Configurations

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