TNETV1644ZDU6 datasheet(292/306 Pages) TI1

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VLYNQ_CLK

VLYNQ_TXD[3:0]

VLYNQ_RXD[3:0]

Data

TMS320DM6437

Digital Media Processor

SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008

www.ti.com

Table 6-109. Timing Requirements for Receive Data for the VLYNQ Module(1) (see Figure 6-54)

-7/-6/-5/-4

-L/-Q6/-Q5/-Q4

NO.

UNIT

MIN

MAX

RTM disabled, RTM sample = 3

1.75

Setup time, VLYNQ_RXD[3:0] valid before

tsu(RXDV-VCLKH)

VLYNQ_CLK high

RTM enabled

(1)

RTM disabled, RTM sample = 3

Hold time, VLYNQ_RXD[3:0] valid after

th(VCLKH-RXDV)

VLYNQ_CLK high

RTM enabled

(1)

The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in

traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see Table 6-110). When

RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.

Table 6-110. RTM RX Data Flop Hold/Setup Timing

Constraints (Typical Values)

RX Data Flop

HOLD (Y)

SETUP (X)

1.3

0.9

1.4

0.7

1.5

-0.4

1.6

-0.6

1.8

-0.8

2.0

-1.0

2.2

-1.1

2.4

-1.2

Figure 6-54. VLYNQ Transmit/Receive Timing

292

Peripheral Information and Electrical Specifications

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