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TNETV1644ZDU6 Datasheet(PDF) 289 Page - Texas Instruments |
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TNETV1644ZDU6 Datasheet(HTML) 289 Page - Texas Instruments |
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289 / 306 page  6.22 VLYNQ 6.22.1 VLYNQ Peripheral Register Description(s) TMS320DM6437 Digital Media Processor www.ti.com SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008 The DM6437 VLYNQ peripheral provides a high speed serial communications interface with the following features. • Low Pin Count • Scalable Performance / Support • Simple Packet Based Transfer Protocol for Memory Mapped Access – Write Request / Data Packet – Read Request Packet – Read Response Data Packet – Interrupt Request Packet • Supports both Symmetric and Asymmetric Operation – Tx pins on first device connect to Rx pins on second device and vice versa – Data pin widths are automatically detected after reset – Request packets, response packets, and flow control information are all multiplexed and sent across the same physical pins – Supports both Host/Peripheral and Peer to Peer communication • Simple Block Code Packet Formatting (8b/10b) • In Band Flow Control – No extra pins needed – Allows receiver to momentarily throttle back transmitter when overflow is about to occur – Uses built in special code capability of block code to seamlessly interleave flow control information with user data – Allows system designer to balance cost of data buffering versus performance • Multiple outstanding transactions • Automatic packet formatting optimizations • Internal loop-back mode Table 6-105. VLYNQ Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0x01E0 1000 - Reserved 0x01E0 1004 CTRL VLYNQ Local Control Register 0x01E0 1008 STAT VLYNQ Local Status Register 0x01E0 100C INTPRI VLYNQ Local Interrupt Priority Vector Status/Clear Register 0x01E0 1010 INTSTATCLR VLYNQ Local Unmasked Interrupt Status/Clear Register 0x01E0 1014 INTPENDSET VLYNQ Local Interrupt Pending/Set Register 0x01E0 1018 INTPTR VLYNQ Local Interrupt Pointer Register 0x01E0 101C XAM VLYNQ Local Transmit Address Map Register 0x01E0 1020 RAMS1 VLYNQ Local Receive Address Map Size 1 Register 0x01E0 1024 RAMO1 VLYNQ Local Receive Address Map Offset 1 Register 0x01E0 1028 RAMS2 VLYNQ Local Receive Address Map Size 2 Register 0x01E0 102C RAMO2 VLYNQ Local Receive Address Map Offset 2 Register 0x01E0 1030 RAMS3 VLYNQ Local Receive Address Map Size 3 Register 0x01E0 1034 RAMO3 VLYNQ Local Receive Address Map Offset 3 Register 0x01E0 1038 RAMS4 VLYNQ Local Receive Address Map Size 4 Register 0x01E0 103C RAMO4 VLYNQ Local Receive Address Map Offset 4 Register Submit Documentation Feedback Peripheral Information and Electrical Specifications 289 |
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