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TNETV2664FIBZWT Datasheet(PDF) 206 Page - Texas Instruments

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No. de pieza TNETV2664FIBZWT
Descripción Electrónicos  Fixed-Point Digital Signal Processor
PDF  249 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TNETV2664FIBZWT Datasheet(HTML) 206 Page - Texas Instruments

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TMS320C6424
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
www.ti.com
6.14.1.3
McASP0 Electrical Data/Timing
6.14.1.3.1
Multichannel Audio Serial Port (McASP) Timing
Table 6-53. Timing Requirements for McASP (see Figure 6-32 and Figure 6-33)(1)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
UNIT
MIN
MAX
1
tc(AHCKRX)
Cycle time, AHCLKR/X
25
ns
2
tw(AHCKRX)
Pulse duration, AHCLKR/X high or low
10
ns
3
tc(CKRX)
Cycle time, ACLKR/X(2)
ACLKR/X ext
25
ns
4
tw(CKRX)
Pulse duration, ACLKR/X high or low
ACLKR/X ext
10
ns
ACLKR/X int
11
ns
5
tsu(FRX-CKRX)
Setup time, AFSR/X input valid before ACLKR/X latches data
ACLKR/X ext
3
ns
ACLKR/X int
0
ns
ACLKR/X ext
4
ns
6
th(CKRX-FRX)
Hold time, AFSR/X input valid after ACLKR/X latches data
input
ACLKR/X ext
6
ns
output
ACLKR/X int
11
ns
7
tsu(AXR-CKRX)
Setup time, AXR input valid before ACLKR/X latches data
ACLKR/X ext
3
ns
ACLKR/X int
3
ns
ACLKR/X ext
4
ns
8
th(CKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
input
ACLKR/X ext
6
ns
output
(1)
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
(2)
There is a clock ratio requirement between the system infrastructure clock, SYSCLK3, and the McASP0 bit clocks, ACLKR/ACLKX. For
proper device operation, the ACLKR/ACLKX frequency must be no faster than ½ of SYSCLK3 frequency.
206
Peripheral Information and Electrical Specifications
Copyright © 2007–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320C6424



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