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TNETV2664FIBZWT Datasheet(PDF) 189 Page - Texas Instruments

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No. de pieza TNETV2664FIBZWT
Descripción Electrónicos  Fixed-Point Digital Signal Processor
PDF  249 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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TNETV2664FIBZWT Datasheet(HTML) 189 Page - Texas Instruments

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TMS320C6424
www.ti.com
SPRS347D – MARCH 2007 – REVISED DECEMBER 2009
6.12.3 HPI Electrical Data/Timing
Table 6-36. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-23 through
Figure 6-24)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
UNIT
MIN
MAX
1
tsu(SELV-HSTBL)
Setup time, select signals(3) valid before HSTROBE low
5
ns
2
th(HSTBL-SELV)
Hold time, select signals(3) valid after HSTROBE low
2
ns
3
tw(HSTBL)
Pulse duration, HSTROBE active low
15
ns
4
tw(HSTBH)
Pulse duration, HSTROBE inactive high between consecutive accesses
2M
ns
11
tsu(HDV-HSTBH)
Setup time, host data valid before HSTROBE high
5
ns
12
th(HSTBH-HDV)
Hold time, host data valid after HSTROBE high
0
ns
Hold time, HSTROBE high after HRDY low. HSTROBE should not be
13
th(HRDYL-HSTBL)
inactivated until HRDY is active (low); otherwise, HPI writes will not
0
ns
complete properly.
(1)
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2)
M = SYSCLK3 period = (CPU clock frequency)/6 in ns. For example, when running parts at 600 MHz, use M = 10 ns .
(3)
Select signals include: HCNTL[1:0], HR/W and HHWIL.
Copyright © 2007–2009, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
189
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Product Folder Link(s): TMS320C6424



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