CC1150-RTY1 datasheet(31/67 Pages) TI1

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CHANSPC _ E 2

XOSC

carrier

FREQ

CHAN

256

CHANSPC _ M

NUM_TXBYTES

GDO

CC1150

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SWRS037B – JANUARY 2006 – REVISED MARCH 2015

Figure 5-15. FIFO_THR=13 versus Number of Bytes in FIFO

5.13 Frequency Programming

The frequency programming in CC1150 is designed to minimize the programming needed in a channel-

oriented system.

To set up a system with channel numbers, the desired channel spacing is programmed with the

MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are

mantissa and exponent respectively.

The base or start frequency is set by the 24-bit frequency word located in the FREQ2, FREQ1 and

FREQ0 registers. This word will typically be set to the centre of the lowest channel frequency that is to be

used.

The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN,

which is multiplied by the channel offset. The resultant carrier frequency is given by Equation 5.

(5)

With a 26-MHz crystal, the maximum channel spacing is 405 kHz. To get, for example, 1-MHz channel

spacing on solution is to use 333-kHz channel spacing and select each third channel in CHANNR.CHAN.

If any frequency programming register is altered when the frequency synthesizer is running, the

synthesizer may give an undesired response. Hence, the frequency programming should only be updated

when the radio is in the IDLE state.

5.14 VCO

The VCO is completely integrated on-chip.

5.14.1 VCO and PLL Self-Calibration

The VCO characteristics will vary with temperature and supply voltage changes, as well as the desired

operating frequency. In order to ensure reliable operation, CC1150 includes frequency synthesizer self-

calibration circuitry. This calibration should be done regularly, and must be performed after turning on

power and before using a new frequency (or channel). The number of XOSC cycles for completing the

PLL calibration is given in Table 5-6.

The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated

each time the synthesizer is turned on, or each time the synthesizer is turned off. This is configured with

the MCSM0.FS_AUTOCAL register setting.

In manual mode, the calibration is initiated when the SCAL command strobe is activated in the IDLE

mode.

The calibration values are not maintained in sleep mode. Therefore, the CC1150 must be recalibrated

after reprogramming the configuration registers when the chip has been in the SLEEP state.

To check that the PLL is in lock the user can program register IOCFGx.GDOx_CFG to 0x0A and use the

lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0, 1, or 2). A positive

transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register

FSCAL1. The PLL is in lock if the register content is different from 0x3F. See more information in the

CC1150 Errata Notes [8].

For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL

lock is achieved if the PLL does not lock the first time.

Detailed Description

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