Engineering Bulletin

Watchdog Operation

EB413

MOTOROLA

7

Watchdog Operation

The watchdog is the computer operating properly (COP) function that

forces a reset of the HC05 device if the counter is not cleared before it

overflows. The timeout of the counter varies between devices, but in

most cases the RESET pin is driven low for a short time when the COP

times out and thus resets the HC05. The timing of the COP reset is

shown in Power-On Reset and External Reset Timing for the

MC68HC05J1. There is no oscillator start-up delay, and so the reset

vectors are fetched within 3 cycles of reset going high.

Some HC05 devices have no buffering internally and so the external

voltage seen on the RESET pin is the actual signal that forces the reset.

More recently designed HC05 devices have the reset signal from the

COP buffered internally so that the external load has no effect on the

COP reset timing or functionality.

With unbuffered COP output on the RESET pin, the maximum external

capacitance or minimum possible pullup resistance on the RESET pin

are critical as these determine the timing and level of the COP reset

output signal.

Check the data sheet for details of the HC05 device COP function but,

where there is any uncertainty a good working limit is a maximum

capacitance of 1

µF and a minimum pullup impedance of 2 kΩ.

EEPROM On Chip

Integrating EEPROM into the HC05 device is increasingly common but

may cause several problems during power up and power down.

Normally the EEPROM array would be initialized, at least in part, during

the production phase. The application normally makes further writes to

the EEPROM in addition to reading the data and so it is unlikely that the

EEPROM could be physically protected from unexpected writing.

Certain conditions such as partial power loss can cause the HC05 to run

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com