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MPC8248VRP Datasheet(PDF) 26 Page - Motorola, Inc |
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MPC8248VRP Datasheet(HTML) 26 Page - Motorola, Inc |
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26 / 56 page ![]() 26 MPC8272 PowerQUICC II™ Family Hardware Specifications MOTOROLA PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE Clock Configuration Modes Clock Configuration Modes 1101_000 100.0 133.3 2.5 250.0 333.3 3 300.0 400.0 5 50.0 66.7 1101_001 100.0 133.3 2.5 250.0 333.3 3.5 350.0 466.6 5 50.0 66.7 1101_010 100.0 133.3 2.5 250.0 333.3 4 400.0 533.3 5 50.0 66.7 1101_011 100.0 133.3 2.5 250.0 333.3 4.5 450.0 599.9 5 50.0 66.7 1101_100 100.0 133.3 2.5 250.0 333.3 5 500.0 666.6 5 50.0 66.7 1101_101 125.0 166.7 2 250.0 333.3 3 375.0 500.0 5 50.0 66.7 1101_110 125.0 166.7 2 250.0 333.3 4 500.0 666.6 5 50.0 66.7 1110_000 100.0 133.3 3 300.0 400.0 3.5 350.0 466.6 6 50.0 66.7 1110_001 100.0 133.3 3 300.0 400.0 4 400.0 533.3 6 50.0 66.7 1110_010 100.0 133.3 3 300.0 400.0 4.5 450.0 599.9 6 50.0 66.7 1110_011 100.0 133.3 3 300.0 400.0 5 500.0 666.6 6 50.0 66.7 1110_100 100.0 133.3 3 300.0 400.0 5.5 550.0 733.3 6 50.0 66.7 1100_000 Reserved 1100_001 Reserved 1100_010 Reserved 1 The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency guarantees the required minimum CPU operating frequency. Minimum CPU frequency is determined by the clock mode. For modes with a CPU multiplication factor ≤ 3, the minimum CPU frequency is 125 MHz or 150 MHz, as shown in the table. For modes with a CPU multiplication factor ≥ 3.5, the minimum CPU frequency is 250 MHz. The “high” values are for the purpose of illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s device. 2 PCI_MODCK determines the PCI clock frequency range. Refer to Table 16 for lower range configurations. 3 MODCK_H = hard reset configuration word [28–31] (refer to Section 5.4 in the MPC8260 User’s Manual). MODCK[1-3] = three hardware configuration pins. 4 CPM multiplication factor = CPM clock/bus clock 5 CPU multiplication factor = Core PLL multiplication factor Table 15. Clock Configurations for PCI Host Mode (PCI_MODCK=0) 1, 2 (continued) Mode 3 Bus Clock (MHz) CPM Multiplication Factor 4 CPM Clock (MHz) CPU Multiplication Factor 5 CPU Clock (MHz) PCI Division Factor PCI Clock (MHz) MODCK_H- MODCK[1-3] Low High Low High Low High Low High Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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