MPC8248VRP datasheet(22/56 Pages) MOTOROLA

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MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Clock Configuration Modes

Clock Conﬁguration Modes

As shown in Table 14, the clocking mode is set according to two sources:

•

PCI_CFG[0]— An input signal. Also deﬁned as “PCI_HOST_EN.” Refer to the Chapter 6,

“External Signals,” and Chapter 9, “PCI Bridge,” in the MPC8272 PowerQUICC II™ Family

Reference Manual.

•

PCI_MODCK—Bit 27 in the Hard Reset Conﬁguration Word. Refer to Chapter 5, “Reset,” in the

MPC8272 PowerQUICC II™ Family Reference Manual.

Within each mode, the conﬁguration of bus, core, PCI, and CPM frequencies is determined by seven bits

during the power-on reset—three hardware conﬁguration pins (MODCK[1–3]) and four bits from hardware

conﬁguration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to the selected

clock operation mode as described in the following sections.

NOTE

Clock conﬁgurations change only after PORESET is asserted.

NOTE: Tval (Output Hold)

The minimum Tval = 2 when PCI_MODCK = 1, and the minimum

Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock

conﬁgurations that ﬁt this condition to achieve PCI-compliant AC timing.

7.1

PCI Host Mode

Table 15 and Table 16 show conﬁgurations for PCI host mode. The frequency values listed are for the

purpose of illustration only. Users must select a mode and input bus frequency so that the resulting

conﬁguration does not exceed the frequency rating of the user’s device. Note that in PCI host mode the input

clock is the bus clock.

Table 14. MPC8272 Clocking Modes

Pins

Clocking Mode

PCI Clock Frequency

Range (MHZ)

Reference

PCI_CFG[0] 1

1 PCI_HOST_EN

PCI_MODCK 2

2 Determines PCI clock frequency range.

PCI host

50–66

Table 15

25–50

Table 16

PCI agent

50–66

Table 17

25–50

Table 18

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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