BQ76PL536APAPR datasheet(32/74 Pages) TI1

32 / 74 page

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

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7.3.6.5 CRC Algorithm

The cyclic redundancy check (CRC) is a CRC-8 error-checking byte, calculated on all the message bytes

(including addresses). It is identical in structure to the SMBus 2.0 packet error check (PEC), and is also known

as the ATM-8 CRC. The CRC is appended to the message for all SPI packets by the device that supplied the

data as the last byte in the packet (when IO_CONTROL[CRC] == 1).

Each bus transaction requires a CRC calculation by both the transmitter and receiver within each packet. The

CRC is calculated in a way that conforms to the polynomial, C(x) = x8 + ×2 + x1 + 1 and must be calculated in the

order of the bits as received, MSB first. The CRC calculation includes all bytes in the transmission, including

address, command, and data. When reading data from the device, the CRC is based on the ADDRESS +

FIRST_REGISTER + LENGTH + returned_device_data[n]. The stuff-bytes used to clock out the data from the IC

are not used as part of the calculation, although if the value 0x00 is used, the 0s have no effect on the CRC.

CRC verification is performed by the receiver when the CS_x line goes false, indicating the end of a packet. If

the CRC verification fails, the message is ignored (discarded), the CRC failure flag is set in the

FAULT_STATUS[CRC] register, and the FAULT line becomes asserted and latched until the error is read and

cleared by the host.

The CRC bit returned in the FAULT_STATUS register reflects the last packet received, not the CRC condition of

the packet reading the FAULT_STATUS contents. CRC errors should be handled at a high priority by the host

controller, before writing to additional registers.

7.3.6.6 Data Packet Usage Examples

The bq76PL536A can be enabled via the host to read just the specific voltage data which would require a total of

2 written bytes (chip address and R/W [#1] + first (starting) register offset [#2]) + LENGTH [#3] and 13 <null>

stuff bytes (12 [n] data bytes + CRC).

The data packet can be expanded periodically to accommodate temperature and GPAI readings as well as

device status as needed by changing the REGISTER_FIRST offset and LENGTH values.

7.3.7 Device Addressing

Each individual device in the series stack requires an address to allow communication with it. Each bq76PL536A

has a CS_S and CS_N that are used in assigning addresses. Once addresses have been assigned, the normal

operation of the CS_N/S lines is asserted (logic high) during communications, and the appropriate bq76PL536A

in the stack responds according to the address transmitted as part of the packet (Figure 22).

When the bq76PL536A is reset, the DEVICE_STATUS[AR] (address request) flag is cleared, the address

CS_N signal is forced to a de-asserted state (CS is not passed north when an address = 0). In this manner, after

a reset the host is assured that a response at address 0x00 is from the first physical device in the stack. After

address assignment of the current device, the host is assured that the next response at address 0x00 is from the

next physical device in the stack.

Once a valid address is assigned to the device, the CS_N signal responds normally, and follows the CS_H or

CS_S signal, propagating to the next device in the stack. Valid addresses are in the range 0x01 through 0x3e.

0x00 is reserved for device discovery after reset. 0x3f is reserved as a broadcast address for all devices.

NOTE

Designer Note: Broadcast messages are only received by devices with a valid address,

and the next higher device. Any device with an address of 0x00 blocks messages to

devices above it. A broadcast message may not be received by all devices in a stack in

situations where some devices do not have a valid address.

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