BQ76PL536APAPR datasheet(30/74 Pages) TI1

30 / 74 page

StartReg Address

Device Address

ReadLengthn

ReadData 1

R/W

ReadDatan

CRC

ReadPacket

CS Assertion

DEV ADDR

1 byte

time

REG ADDR

CNT = n

0x00

READn...

CRC

n + 1 placeholderbytes

SDI

SDO

0x00

bq76PL536A

SLUSAD3B – JUNE 2011 – REVISED JANUARY 2016

www.ti.com

The number of devices in the vertical stack and other factors limit the maximum SCLK frequency. Each device

imposes an approximately 30-ns delay on the round trip communications speed, that is, from SCLK rising (an

input to all devices) to the SDO pin transitioning requires approximately 30 ns per device. The designer must add

to this the delay caused by the PCB trace (in turn determined by the material and layout), any connectors in

series with the connection, and any other wiring or cabling between devices in the system. To maximize speed,

these other system components should be carefully selected to minimize delays and other detrimental effects on

signal quality. Wiring and connectors should receive special attention to their transmission line characteristics.

Other factors which should be considered are clock duty cycle, clock jitter, temperature effects on clock and

system components, user-selected drive level for the level-shift interface, and desired design margin.

The VBUS SPI interface is placed in a low-power mode when CS_H is not asserted on the base device.

The CS_N/S pins are asserted by a logic high on the vertical interface bus (logically inverted from CS_H). This

creates a default VBUS CS condition of logic low, reducing current consumption to a minimum.

To reduce power consumption of the SPI interface to a minimum, the SCLK_H and SDI_H should be maintained

at a logic low (de-asserted) while CS_H is asserted (low). Most SPI buses are operated this way by

microcontrollers. The VBUS versions of these signals are not inverted from the host interface. The device also

de-asserts by default the SDO_N/S pins to minimize power consumption.

7.3.6 Packet Formats

7.3.6.1 Data Read Packet

When the bq76PL536A is selected (CS_S [CS_H for first device] is active and the bq76PL536A has been

addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N

pin of the next device down the stack. This continues to the first device in the stack, where the data in from the

SDO_N pin is transmitted to the host via the SDO_H pin. The device supplying the read data generates a CRC

as the last byte sent. See Figure 18 and Figure 19 for additional information.

Figure 18. READ Packet Format

Figure 19. READ Packet Detail

Submit Documentation Feedback

Product Folder Links: bq76PL536A

BQ76PL536APAPR Datasheet(PDF) 30 Page - Texas Instruments

BQ76PL536APAPR Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Descarga

Enlace URL