MEC1322 datasheet(185/456 Pages) MICROCHIP

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DS00001719D-page 185

MEC1322

14.11.7

INTERRUPT IDENTIFICATION REGISTER

By accessing this register, the host CPU can determine the highest priority interrupt and its source. Four levels of priority

interrupt exist. They are in descending order of priority:

Receiver Line Status (highest priority)

Received Data Ready

Transmitter Holding Register Empty

MODEM Status (lowest priority)

Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Iden-

tification Register (refer to Table 14-13). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indi-

cates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port records new

interrupts, the current indication does not change until access is completed. The contents of the IIR are described below.

0 EXRF

Enable XMIT and RECV FIFO. Setting this bit to a logic “1” enables

both the XMIT and RCVR FIFOs. Clearing this bit to a logic “0” dis-

ables both the XMIT and RCVR FIFOs and clears all bytes from both

FIFOs. When changing from FIFO Mode to non-FIFO (16450) mode,

data is automatically cleared from the FIFOs. This bit must be a 1

when other bits in this register are written to or they will not be prop-

erly programmed.

W0h

RESET

TABLE 14-12: RECV FIFO TRIGGER LEVELS

Bit 7

Bit 6

RECV FIFO

Trigger Level (BYTES)

114

Offset

02h

Bits

Description

Type

Default

Reset

Event

7:6 FIFO_EN

These two bits are set when the FIFO CONTROL Register bit 0

equals 1.

R0h

RESET

5:4 Reserved

3:1 INTID

These bits identify the highest priority interrupt pending as indicated

by Table 14-13, "Interrupt Control Table". In non-FIFO mode, Bit[3] is

a logic “0”. In FIFO mode Bit[3] is set along with Bit[2] when a time-

out interrupt is pending.

R0h

RESET

Offset

02h

Bits

Description

Type

Default

Reset

Event

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