MEC1322 datasheet(75/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 75

MEC1322

5.0

LPC INTERFACE

5.1

Introduction

The Intel® Low Pin Count (LPC) Interface is the LPC Interface used by the system host to configure the chip and com-

municate with the logical devices implemented in the design through a series of read/write registers. Register access is

accomplished through the LPC transfer cycles defined in Table 5-8, "LPC Cycle Types Supported".

The Logical Devices implemented in the design are identified in Table 5-16, “I/O Base Address Registers,” on page 92.

The Base Address Registers allow any logical device’s runtime registers to be relocated in LPC I/O space. All chip con-

figuration registers for the device are accessed indirectly through the LPC I/O Configuration Port (see Section 5.8.3,

"Configuration Port," on page 83).

LPC memory cycles may also be used to access the Base Address Registers of certain devices.

5.2

References

• Intel® Low Pin Count (LPC) Interface Specification, v1.1

• PCI Local Bus Specification, Rev. 2.2

• Serial IRQ Specification for PCI Systems Version 6.0.

• PCI Mobile Design Guide Rev 1.0

5.3

Terminology

This table defines specialized terms localized to this feature.

TABLE 5-1:

TERMINOLOGY

Term

Definition

System Host

Refers to the external CPU that communicates with this device via the LPC Interface.

Logical Devices

Logical Devices are LPC accessible features that are allocated a Base Address and

range in LPC I/O address space

Runtime Register

Runtime Registers are register that are directly I/O accessible by the System Host via

the LPC interface. These registers are defined in Section 5.10, "Runtime Registers,"

on page 93.

Configuration Registers

Registers that are only accessible in CONFIG_MODE. These registers are defined in

Section 5.9, "LPC Configuration Registers," on page 88.

EC_Only Registers

Registers that are not accessible by the System Host. They are only accessible by an

internal embedded controller. These registers are defined in Section 5.11, "EC-Only

Registers," on page 94.

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