SM8211M

NIPPON PRECISION CIRCUITS—10

Lock mode

If the sync code is detected during the preamble

period, device operation transfers to lock mode and

BS1 goes LOW. BS1 then goes HIGH again under

frame timing, where the frame number is set by flags

FF0 to FF2, and the 24 addresses are compared with

ID-ROM (If the frame number is 0, BS1 stays

HIGH). If errors of 2 bits or less occur, the address is

still recognized. Since there are two code words per

frame, this check is done twice.

When one of the 24 addresses does not match, BS1

goes LOW and the device waits for the next sync

code receive timing. If the sync code is still not

detected after two consecutive attempts, device oper-

ation transfers to idle mode, except during message

reception where operation stays in lock mode. If the

sync code is not detected on the second attempt, but

instead a pattern forming a preamble is detected,

device operation transfers to preamble mode and not

idle mode (preamble mode is more advantageous for

sync code detection).

Figure 6. Operating mode transition diagram

Switch-ON mode

Preamble mode

Idle mode

Lock mode

A

B

C

D

E

F

G

A: After RST goes LOW, ID code is read in sync with TX-CLK

B: Rate error or, within a fixed period, preamble pattern or sync code not detected

C: Preamble pattern detected

D: Sync code detected 1 cycle immediately after transferring from lock mode

E: Sync code not detected on 2 consecutive attempts

F: Same as E, but preamble pattern detected on the second attempt

G: Sync code detected

When one of the 24 addresses does match, ADD-

DET goes HIGH for the duration of the next code

word period and the corresponding 5-bit address

information is transmitted to the CPU on RX-DATA

in sync with RX-CLK. When the address informa-

tion is confirmed, BS1 is held HIGH and the mes-

sage is received. The 20-bit error-corrected message

data, a 2-bit error correction result code and an even-

parity bit form a 23-bit word that is sent to the CPU

on RX-DATA in sync with RX-CLK. When an

incoming message spans two or more batches, addi-

tional sync code detection occurs during sync code

receive timing.

Message reception ends when an address code or

idle code is detected, or when interrupted using the

BREAK input. When message reception ends, BS1

goes LOW and the device waits for either the address

detect timing of the next frame or the sync code

receive timing.