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SM8211M Datasheet(PDF) 7 Page - Nippon Precision Circuits Inc |
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SM8211M Datasheet(HTML) 7 Page - Nippon Precision Circuits Inc |
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7 / 22 page ![]() SM8211M NIPPON PRECISION CIRCUITS—7 Idle signal (dummy signal) An idle word can be inserted into either the address or message signal to indicate that the word contains no information. The idle word bit pattern is shown in table 3. Message reception is halted when the receiver detects an idle word. In pager systems that send numeric data, the number of frames varies with the type of message being sent. In this case, an idle signal is transmitted to indicate completion of the message. Receive signal duty factor During preamble detection, the preamble pattern (1,0) is recognized at duty factors from 25% (min) to 75% (max) of the (1,0) preamble cycle. Battery Saving (BS1, BS2, BS3) The SM8211M controls the intermittent-duty opera- tion of the RF stage, which reduces battery consump- tion, and outputs three control signals (BS1, BS2, BS3). The function each signal controls in each mode is described below. s BS1 (RF-control main output signal)—The RF stage is active when BS1 is HIGH. The rising- edge setup time for receive timing is set by flags RF0 to RF5 (60 steps). The maximum setup time is 49.167 ms at 1200 bps, and 115.234 ms at 512 bps. Note that 3C, 3D, 3E and 3F are invalid settings for BS1. s BS2 (RF-control output signal)—BS2 is used to control the discharge of the receive signal DC-cut capacitor. The function of BS2 is determined by flag BS2, as described below. • When flag BS2 is 0, pin BS2 goes HIGH together with BS1 and then goes LOW again after the BS1 setup time. However, in lock mode (during address/message reception), it stays LOW. • When flag BS2 is 1, pin BS2 goes HIGH during lock mode sync code receive timing, and pre- amble mode and idle mode signal receive tim- ing. s BS3 (RF-control output signal)—BS3 is used to control PLL operation when the PLL is used. The rising-edge setup time for receive timing is set by flags PL0 to PL5 (60 steps). The maximum setup time is 50.833 ms at 1200 bps, and 119.141 ms at 512 bps. Note that 3E and 3F are invalid settings for BS3. Note also that (BS3 rising-edge setup time) − (BS1 rising-edge setup time) should be ≥ 2. Table 3. Idle code word Bit number Bit value Bit number Bit value 1 0 17 1 2 1 18 1 3 1 19 0 4 1 20 0 5 1 21 0 6 0 22 0 7 1 23 0 8 0 24 1 9 1 25 1 100260 110270 120281 131290 140301 150311 161321 |
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