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M30620FCAFP Datasheet(PDF) 38 Page - Mitsubishi Electric Semiconductor

No. de pieza M30620FCAFP
Descripción Electrónicos  SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PDF  274 Pages
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Fabricante Electrónico  MITSUBISHI [Mitsubishi Electric Semiconductor]
Página de inicio  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M30620FCAFP Datasheet(HTML) 38 Page - Mitsubishi Electric Semiconductor

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Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
38
Pin
Memory expansion mode
Single-chip mode
Microprocessor mode
_______
_______
Address bus, data bus, CS0 to CS3
Retains status before stop mode
_____
______
________
________
_________
RD, WR, BHE, WRL, WRH
“H”
__________
HLDA, BCLK
“H”
ALE
“H”
Port
Retains status before stop mode Retains status before stop mode
CLKOUT
When fc selected
Valid only in single-chip mode
“H”
When f8, f32 selected
Valid only in single-chip mode
Retains status before stop mode
Table 1.10.2. Port status during stop mode
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4
functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.



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