AS1123 datasheet(19/25 Pages) AMSCO

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AS1123

Datasheet - A p p l i c a t i o n I n f o r m a t i o n

Constant Current

In LED display applications, the AS1123 provides virtually no current variations from channel-to-channel and from AS1123-to-AS1123. This is

mostly due to 2 factors:

While IOUT ³ 10mA, the maximum current skew is less than ±3% between channels and less than ±3% between AS1123 devices.

In the saturation region, the characteristic curve of the output stage is flat. Thus, the output current can be kept constant regardless of the

variations of LED forward voltages (VF).

Adjusting Output Current

The AS1123 scales up the reference current (IREF) set by external resistor (REXT) to sink a current (IOUT) at each output port. As shown the

output current in the saturation region is extremely flat so that it is possible to define it as target current (IOUT TARGET). IOUT TARGET can be

calculated by:

VREXT = 1.253V

(EQ 1)

IREF = VREXT/REXT (if the other end of REXT is connected to ground)

(EQ 2)

IOUT TARGET = IREF*15 = (1.253V/REXT)*15

(EQ 3)

Where:

REXT is the resistance of the external resistor connected to pin REXT.

VREXT is the voltage on pin REXT.

The magnitude of current (as a function of REXT) is around 40mA at 470

Ω and 20mA at 940Ω.

Package Power Dissipation

The maximum allowable package power dissipation (PD) is determined as:

PD(MAX) = (TJ-TAMB)/RTH(J-A)

(EQ 4)

When 16 output channels are turned on simultaneously, the actual package power dissipation is:

PD(ACT) = (IDD*VDD) + (IOUT*Duty*VDS*16)

(EQ 5)

Therefore, to keep PD(ACT)

≤ PD(MAX), the maximum allowed output current as a function of duty cycle is:

IOUT = {[(TJ-TAMB)/RTH(J-A)]-(IDD*VDD)}/VDS/Duty/16

(EQ 6)

Where:

TJ = -40°C to +125°C

Delayed Outputs (only for AS1123B)

The AS1123B has graduated delay circuits between outputs. These delay circuits can be found between OUTNn and the constant current block.

The fixed delay time is 20 ns (typ) where OUTN0:3 has no delay, OUTN4:7 has 20ns delay, OUTN8:11 has 40ns delay and OUTN12:15 has

60ns delay. This delay prevents large inrush currents, which reduce power supply bypass capacitor requirements when the outputs turn on.

Switching-Noise Reduction

LED drivers are frequently used in switch-mode applications which normally exhibit switching noise due to parasitic inductance on the PCB.

Load Supply Voltage

Considering the package power dissipation limits, the AS1123 should be operated within the range of VDS = 0.4 to 1.0V.

For example, if VLED is higher than 5V, VDS may be so high that PD(ACT) > PD(MAX) where VDS = VLED - VF. In this case, the lowest possible

supply voltage or a voltage reducer (VDROP) should be used. The voltage reducer allows

VDS = (VLED -VF) - VDROP.

Note:

Resistors or zener diodes can be used as a voltage reducer as shown in Figure 23 on page 19.

AS1123 Datasheet(PDF) 19 Page - ams AG

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