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STM32F215RE Datasheet(PDF) 19 Page - STMicroelectronics |
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STM32F215RE Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 175 page ![]() DocID17050 Rev 9 19/175 STM32F21xxx Functional overview 174 Figure 5. Multi-AHB matrix 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each. They are able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. They share some centralized FIFOs for APB/AHB peripherals, support burst transfer and are designed to provide the maximum peripheral bandwidth (AHB/APB). The two DMA controllers support circular buffer management, so that no specific code is needed when the controller reaches the end of the buffer. The two DMA controllers also have a double buffering feature, which automates the use and switching of two memory buffers without requiring any special code. Each stream is connected to dedicated hardware DMA requests, with support for software trigger on each stream. Configuration is made by software and transfer sizes between source and destination are independent. ARM Cortex-M3 GP DMA1 GP DMA2 MAC Ethernet USB OTG HS Bus matrix-S S0 S1 S2 S3 S4 S5 S6 S7 ICODE DCODE Flash memory SRAM 112 Kbyte SRAM 16 Kbyte AHB1 periph AHB2 periph FSMC Static MemCtl M0 M1 M2 M3 M4 M5 M6 ai15963c APB1 APB2 |
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