W25Q32FVZPIP datasheet(55/99 Pages) WINBOND

55 / 99 page

W25Q32FV

Publication Release Date: Sept 16,, 2013

- 54 -

Revision H

8.2.19

64KB Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all

1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase

Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low

and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase

instruction sequence is shown in Figure 33a & 33b.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done

the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase

instruction will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle

is in progress, the Read Status Register instruction may still be accessed for checking the status of the

BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished

and the device is ready to accept other instructions again. After the Block Erase cycle has finished the

Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not

be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)

bits or the Individual Block/Sector Locks.

/CS

CLK

(IO

Mode 0

Mode 3

Instruction (D8h)

High Impedance

24-Bit Address

Mode 0

Mode 3

= MSB

Figure 33a. 64KB Block Erase Instruction (SPI Mode)

/CS

CLK

Mode 0

Mode 3

D8h

Instruction

A23-16

A15-8

A7-0

Mode 0

Mode 3

Figure 33b. 64KB Block Erase Instruction (QPI Mode)

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