UCD7201_13 datasheet(4/25 Pages) TI1

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UCD7201

SLUS645E – FEBRUARY 2005 – REVISED NOVEMBER 2009

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ELECTRICAL CHARACTERISTICS (continued)

VDD = 12 V, 4.7-μF capacitor from VDD to GND, 0.22μF from 3V3 to AGND, TA = TJ = -40°C to 105°C, (unless otherwise

noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold

ILIM = OPEN

0.51

0.55

0.58

ILIM maximum current limit threshold

ILIM = 3.3 V

1.05

1.10

1.15

ILIM current limit threshold

ILIM = 0.75 V

0.700

0.725

0.750

ILIM minimum current limit threshold

ILIM = 0.25 V

0.21

0.23

0.25

CLF output high level

CS > ILIM , ILOAD = -7 mA

2.64

CLF output low level

≤ ILIM, ILOAD = 7 mA

0.66

Propagation delay from IN to CLF

IN rising to CLF falling after a current limit event

CURRENT SENSE COMPARATOR

Bias voltage

Includes CS comp offset

Input bias current

–1

μA

Propagation delay from CS to OUTx

ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV

Propagation delay from CS to CLF

ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance

IN = low, resistance from CS to AGND

Ω

OUTPUT DRIVERS

Source current

VDD = 12 V, IN = high, OUTx = 5 V

Sink current

VDD = 12 V, IN = low, OUTx = 5 V

Source current

VDD = 4.75 V, IN = high, OUTx = 0

Sink current

VDD = 4.75 V, IN = low, OUTx = 4.75 V

Rise time, tR

CLOAD= 2.2 nF, VDD = 12 V

Fall time, tF

CLOAD = 2.2 nF, VDD = 12 V

Output with VDD < UVLO

VDD =1.0 V, ISINK = 10 mA

0.8

1.2

Propagation delay from IN to OUT1,

CLOAD = 2.2 nF, VDD = 12 V, CLK rising

tD1

Propagation delay from IN to OUT2,

CLOAD = 2.2 nF, VDD = 12 V, CLK falling

tD2

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