AD7665 datasheet(4/23 Pages) AD

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PRELIMINARY TECHNICAL DATA

–4–

AD7667

Table I. Serial clock timings in Master Read after Convert

DIVSCLK[1]

0011

unit

DIVSCLK[0]

0101

SYNC to SCLK First Edge Delay Minimum

t18

171717ns

Internal SCLK Period minimum

t19

100

200

Internal SCLK Period typical

t19

140

280

Internal SCLK HIGH Minimum

t20

100

Internal SCLK LOW Minimum

t21

214999ns

SDOUT Valid Setup Time Minimum

t22

181818ns

SDOUT Valid Hold Time Minimum

t23

3089ns

SCLK Last Edge to SYNC Delay Minimum

t24

140

300

Busy High Width Maximum (Warp)

t24

1.5

5.25

µs

Busy High Width Maximum (Normal)

t24

1.75

2.25

3.25

5.55

µs

Busy High Width Maximum (Impulse)

t24

2.5

3.5

5.75

µs

REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)

External SCLK Setup Time

t31

5ns

External SCLK Active Edge to SDOUT Delay

t32

318

SDIN Setup Time

t33

5ns

SDIN Hold Time

t34

5ns

External SCLK Period

t35

External SCLK HIGH

t36

External SCLK LOW

t37

NOTES

1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C

L of 10 pF; otherwise, the load is 60 pF maximum.

3In serial master read during convert mode. See Table I for serial master read after convert mode.

Specifications subject to change without notice.

Symbol

Min

Typ

Max

Unit

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