REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–19–

CS

BYTE

Pins D[15:8]

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

HI-Z

HIGH BYTE

LOW BYTE

HI-Z

t12

t12

t13

Pins D[7:0]

RD

Figure TBD, 8-bit Parallel Interface

CS = 0

CNVST

,

RD

BUSY

PREVIOUS

CONVERSION

DATA

BUS

Figure 15. Slave Parallel Data Timing for Reading

(Read During Convert)

SERIAL INTERFACE

The AD7667 is configured to use the serial interface when

the SER/

PAR is held high. The AD7667 outputs 16 bits of

data, MSB first, on the SDOUT pin. This data is synchro-

nized with the 16 clock pulses provided on SCLK pin. The

output data is valid on both the rising and falling edge of the

data clock.

MASTER SERIAL INTERFACE

Internal Clock

The AD7667 is configured to generate and provide the serial

data clock SCLK when the EXT/

INT pin is held low. The

AD7667 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted if desired. Depending on RDC/

SDIN input, the data can be read after each conversion or

during the following conversion. Figure 16 and Figure 17

show the detailed timing diagrams of these two modes.

Usually, because the AD7667 is used with a fast throughput,

the mode master, read during conversion is the most recom-

mended serial mode when it can be used.

In read-during-conversion mode, the serial clock and data

toggle at appropriate instants which minimize potential

feedthrough between digital activity and the critical conver-

sion decisions.

In read-after-conversion mode, it should be noted that, unlike in

other modes, the signal BUSY returns low after the 16 data bits

are pulsed out and not at the end of the conversion phase which

results in a longer BUSY width.

SLAVE SERIAL INTERFACE

External Clock

The AD7667 is configured to accept an externally supplied

serial data clock on the SCLK pin when the EXT/

INT pin is

held high. In this mode, several methods can be used to read

the data. The external serial clock is gated by

CS. When CS and

RD are both low, the data can be read after each conversion

or during the following conversion. The external clock can be

either a continuous or discontinuous clock. A discontinuous

clock can be either normally high or normally low when inac-

tive. Figure 18 and Figure 20 show the detailed timing diagrams

of these methods.

While the AD7667 is performing a bit decision, it is impor-

tant that voltage transients not occur on digital input/output

pins or degradation of the conversion result could occur.

This is particularly important during the second half of the

conversion phase because the AD7667 provides error cor-

rection circuitry that can correct for an improper bit

SDOUT

CS

SCLK

D1

D0

X

D15

D14

D13

1

2

3

141516

CNVST

BUSY

EXT/INT = 1

INVSCLK = 0

RD = 0

Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)