REV. PrA

PRELIMINARY TECHNICAL DATA

AD7667

–5–

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7667 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature

Model

Range

Package Description

Package Option

AD7667AST

–40°C to +85°C

Quad Flatpack (LQFP)

ST-48

AD7667ASTRL

–40°C to +85°C

Quad Flatpack (LQFP)

ST-48

AD7667ACP

–40°C to +85°C

Chip Scale (LFCSP)

CP-48

AD7667ACPRL

–40°C to +85°C

Chip Scale (LFCSP)

CP-48

EVAL-AD7667CB

1

Evaluation Board

EVAL-CONTROL BRD2

2

Controller Board

NOTES

ABSOLUTE MAXIMUM RATINGS

*

IN

. . . . . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V

Ground Voltage Differences

AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ±0.3 V

Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . .

-0.3V to +7 V

AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . ±7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . .

-0.3V to +7 V

Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 3.0 V

Internal Power Dissipation

3

. . . . . . . . . . . . . . . . . . . 700 mW

Internal Power Dissipation

4

. . . . . . . . . . . . . . . . . . . . . 2.5 W

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range

(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

NOTES

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

48-Lead LQFP;

θ

48-Lead LFCSP;

θ

500 A

1.6mA

TO OUTPUT

PIN

1.4V

60pF*

*

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND

SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD

Figure 1. Load Circuit for Digital Interface Timing,

0.8V

2V

2V

0.8V

0.8V

2V

t

DELAY

t

DELAY

Figure 2. Voltage Reference Levels for Timing

WARNING!

ESD SENSITIVE DEVICE