PXS30 datasheet(10/139 Pages) FREESCALE

10 / 139 page

PXS30 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Introduction

Freescale Semiconductor

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Configurable bus speed modes

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Support for 2 MB address space

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Chip select and write/byte enable options as presented in the pin-muxing table in Section 2,

Package pinouts and signal descriptions

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Configurable wait states (via chip selects)

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Optional automatic CLKOUT gating to save power and reduce EMI

1.5.8

On-chip flash memory

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Up to 2 MB Code flash memory with ECC

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64 KB Data flash memory with ECC

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Censorship protection scheme to prevent flash content visibility

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Multiple block sizes to support features such as boot block, operating system block, and EEPROM

emulation

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Read-while-write with multiple partitions

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Parallel programming mode to support rapid end of line programming

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Hardware programming state machine

1.5.9

Cache memory

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Harvard architecture cache

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16 KB instruction / 16 KB data

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Four-way set-associative Harvard (instruction and data) 256-bit long cache

— Two 32-bit fetches per clock

— Eight-entry store buffer

— Way locking

— Supports tag and data parity

1.5.10

On-chip internal static RAM (SRAM)

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Up to 512 KB general-purpose SRAM

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ECC performs single-bit correction, double-bit error detection

— Address included in ECC checkbase

1.5.11

DRAM controller

The DRAM controller (available only on 473-pin devices) is a multi-port controller that monitors

incoming requests on the three AHB slave ports and decides (at each rising clock edge) what command

needs to be sent to the external DRAM.

The DRAM controller on this device supports the following types of memories:

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Mobile DDR (mDDR)

PXS30 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

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