PXS30 datasheet(4/139 Pages) FREESCALE

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PXS30 Microcontroller Data Sheet, Rev. 1

Preliminary—Subject to Change Without Notice

Introduction

Freescale Semiconductor

1.3

Block diagram

Figure 1 shows a top-level block diagram of the PXS30 device.

Clocking

Clock monitor unit

(CMU)

3 modules

Clock output

2 modules

Frequency-modulated

phase-locked loop

(FMPLL)

2 modules (system and auxiliary)

IRCOSC – 16 MHz

XOSC 4 MHz – 40 MHz

Supply

Power management unit

(PMU)

Yes

1.2 V low-voltage

detector (LVD12)

1.2 V high-voltage

detector (HVD12)

2.7 V low-voltage

detector (LVD27)

Debug

Nexus

Class 3+ (for cores and SRAM ports)

Packages

MAPBGA

257 pins

473 pins

Temperature

Ambient

See the TA recommended operating condition in the device data sheet

NOTES:

1 Sphere of Replication.

2 Does not include Test or Shadow Flash memory space.

3 Available only on 473-pin package.

4 DDR available only on 473 package. Other modules available as follows:

EBI or DDR on 473 package.

EBI + PDI on 473 package.

DDR + PDI on 473 package

PDI only on 257 package.

Table 1. PXS30 Family Feature Set (continued)

Features

PXS3010

PXS3015

PXS3020

PXS30 Datasheet(PDF) 4 Page - Freescale Semiconductor, Inc

PXS30 Datasheet(HTML) 4 Page - Freescale Semiconductor, Inc

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