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PXS30 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc |
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PXS30 Datasheet(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 139 page  Package pinouts and signal descriptions PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Freescale Semiconductor 21 Figure 5. PXS30 473 MAPBGA pinout (northeast, viewed from above) Figure 6. PXS30 473 MAPBGA pinout (southeast, viewed from above) 13 14 15 16 17 18 19 20 21 22 23 fec TXD[3] VDD_ HV_IO pdi DATA[3] pdi DATA[1] pdi CLOCK pdi DATA[7] pdi DATA[10] pdi DATA[13] pdi DATA[15] VSS_ HV_IO VSS_ HV_IO A fec TX_ER VSS_ HV_IO pdi DATA[6] pdi DATA[4] pdi DATA[0] pdi LINE_V pdi DATA[9] pdi DATA[14] can0 TXD VDD_ HV_IO VSS_ HV_IO B fec RX_CLK fec RXD[1] fec COL pdi DATA[5] pdi DATA[2] pdi DATA[8] pdi DATA[12] can0 RXD VSS_ HV_PDI siul GPIO[197] dramc CAS C VDD_ HV_FLA fec RXD[2] fec MDC VDD_ HV_PDI VSS_ HV_PDI pdi DATA[11] pdi FRAME_V VDD_ HV_PDI dramc BA[1] siul GPIO[195] dramc BA[0] D mc_cgl clk_out siul GPIO[149] dramc CS0 dramc BA[2] E VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR dramc RAS siul GPIO[194] siul GPIO[148] dramc D[5] F VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR siul GPIO[196] dramc DQS[0] dramc DM[0] dramc D[7] G VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc D[2] VDD_HV_ DRAM_VTT VDD_HV_ DRAM VSS_HV_ DRAM H VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc D[0] dramc D[1] dramc D[3] dramc D[6] J VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VSS_ HV_IO dramc D[4] dramc D[8] dramc D[9] K VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VDD_ HV_IO VDD_HV_ DRAM_VTT VSS_HV_ DRAM VDD_HV_ DRAM L VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc ODT dramc WEB dramc D[11] dramc D[10] M VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc DQS[1] dramc DM[1] dramc D[13] dramc D[12] N VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc D[14] dramc D[15] VSS_HV_ DRAM VDD_HV_ DRAM P VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR VDD_HV_ DRAM_VREF dramc ADD[3] dramc CKE dramc CLKB R VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc ADD[8] dramc ADD[9] dramc ADD[1] dramc CLK T VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VSS_ LV_COR VDD_ LV_COR dramc ADD[6] dramc ADD[12] VDD_HV_ DRAM dramc ADD[0] U VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR VDD_ LV_COR lin0 TXD dramc ADD[13] VSS_HV_ DRAM dramc ADD[2] V lin0 RXD dramc ADD[14] dramc ADD[7] dramc ADD[4] W VDD_ HV_IO adc0_adc1 AN[11] etimer1 ETC[5] etimer1 ETC[4] adc1 AN[8] adc1 AN[6] TCK VDD_HV_IO dramc ADD[15] dramc ADD[11] dramc ADD[5] Y adc0 AN[8] adc0_adc1 AN[12] adc1 AN[0] adc1 AN[2] adc1 AN[5] adc1 AN[7] TDI etimer1 ETC[0] VSS_HV_IO lin1 TXD dramc ADD[10] AA adc0 AN[7] adc0_adc1 AN[13] adc1 AN[1] adc1 AN[3] adc1 AN[4] TDO TMS RESERVED lin1 RXD VDD_ HV_IO VSS_ HV_IO AB VSS_ HV_ADR_0 adc0_adc1 AN[14] VDD_ HV_ADR_1 VSS_ HV_ADR_1 VDD_ HV_PMU VREG_CTRL VSS_ HV_PMU RESET_ SUP VREG_INT_ ENABLE VSS_ HV_IO VSS_ HV_IO AC 13 14 15 16 17 18 19 20 21 22 23 |
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