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STM32F407IE Datasheet(PDF) 66 Page - STMicroelectronics

No. de pieza STM32F407IE
Descripción Electrónicos  USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
PDF  154 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F407IE Datasheet(HTML) 66 Page - STMicroelectronics

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Electrical characteristics
STM32F405xx, STM32F407xx
66/154
Doc ID 022152 Rev 1
Table 18.
Typical and maximum current consumption in Sleep mode(1)
Symbol
Parameter
Conditions
fHCLK
Typ
Max(2)
Unit
TA = 25 °C TA = 85 °C
TA =
105 °C
IDD
Supply current in
Sleep mode
External clock(3),
all peripherals enabled(4)
168 MHz
TBD
TBD
TBD
mA
144 MHz
TBD
TBD
TBD
120 MHz
38
TBD
TBD
90 MHz
30
TBD
TBD
60 MHz
20
TBD
TBD
30 MHz
11
TBD
TBD
25 MHz
8
TBD
TBD
16 MHz
6
TBD
TBD
8 MHz
3.6
TBD
TBD
4 MHz
2.4
TBD
TBD
2 MHz
1.9
TBD
TBD
External clock(3), all
peripherals disabled
168 MHz
TBD
TBD
TBD
144 MHz
TBD
TBD
TBD
120 MHz
8
TBD
TBD
90 MHz
7
TBD
TBD
60 MHz
5
TBD
TBD
30 MHz
3.5
TBD
TBD
25 MHz
2.5
TBD
TBD
16 MHz
2.1
TBD
TBD
8 MHz
1.7
TBD
TBD
4 MHz
1.5
TBD
TBD
2 MHz
1.4
TBD
TBD
1.
TBD stands for “to be defined”.
2.
Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
3.
External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
4.
Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is on (ADON bit is set in the ADC_CR2 register).



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