ST72325AR7B3 datasheet(182/197 Pages) STMICROELECTRONICS

182 / 197 page

ST72325xx

182/197

ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)

OPT0= FMP_R Flash memory read-out protection

Read-out protection, when selected, provides a

protection against Program Memory content ex-

traction and against write access to Flash memo-

ry.

Erasing the option bytes when the FMP_R option

is selected causes the whole user memory to be

erased first, and the device can be reprogrammed.

Refer to Section 4.3.1 and the ST7 Flash Pro-

gramming Reference Manual for more details.

0: Read-out protection enabled

1: Read-out protection disabled

OPTION BYTE 1

OPT7= PKG1 Package selection bit 1

This option bit selects the package.

Note: On the chip, each I/O port has up to 8 pads.

Pads that are not bonded to external pins are

forced in input pull-up configuration after reset.

The configuration of these pads must be kept at

reset state to avoid added current consumption.

In LQFP48(C) devices (PA0, PA1, PB6, PB7,

PD6, PD7, PE3, PE5, PE6, PE7, PF3, PF5) are in

input floating configuration after reset. Refer to

Note 4 on page 16.

OPT6 = RSTC RESET clock cycle selection

This option bit selects the number of CPU cycles

applied during the RESET phase and when exiting

HALT mode. For resonator oscillators, it is advised

to select 4096 due to the long crystal stabilization

time.

0: Reset phase with 4096 CPU cycles

1: Reset phase with 256 CPU cycles

OPT5:4 = OSCTYPE[1:0] Oscillator Type

These option bits select the ST7 main clock

source type.

OPT3:1 = OSCRANGE[2:0] Oscillator range

When the resonator oscillator type is selected,

these option bits select the resonator oscillator

current source corresponding to the frequency

range of the used resonator. Otherwise, these bits

are used to select the normal operating frequency

range.

OPT0 = PLLOFF PLL activation

This option bit activates the PLL which allows mul-

tiplication by two of the main input clock frequency.

The PLL is guaranteed only with an input frequen-

cy between 2 and 4MHz, for this reason the PLL

must not be used with the internal RC oscillator.

0: PLL x2 enabled

1: PLL x2 disabled

CAUTION: the PLL can be enabled only if the

“OSC RANGE” (OPT3:1) bits are configured to “

2~4MHz”. Otherwise, the device functionality is

not guaranteed.

Version

Selected Package

Flash size

PKG 1

R/AR

LQFP64

32/48/60K

LQFP48(C)

32/48/60K

LQFP44/SDIP42

48/60K

S/J

LQFP48(S)/LQFP44/

SDIP42

16/32K

LQFP32/SDIP32

16/32K

Clock Source

OSCTYPE

Resonator Oscillator

Reserved

Internal RC Oscillator

External Source

Typ. Freq. Range

OSCRANGE

210

1~2MHz

2~4MHz

4~8MHz

8~16MHz

ST72325AR7B3 Datasheet(PDF) 182 Page - STMicroelectronics

ST72325AR7B3 Datasheet(HTML) 182 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL