ST72325AR7B3 datasheet(181/197 Pages) STMICROELECTRONICS

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ST72325xx

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14 ST72325 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro-

grammable versions (FLASH) as well as in factory

coded versions (ROM/FASTROM).

ST72325 devices are ROM versions. ST72P325

devices are Factory Advanced Service Technique

ROM (FASTROM) versions: they are factory-pro-

grammed HDFlash devices. FLASH devices are

shipped to customers with a default content, while

ROM/FASTROM factory coded parts contain the

code supplied by the customer. This implies that

FLASH devices have to be configured by the cus-

tomer using the Option Bytes while the ROM/FAS-

TROM devices are factory-configured.

14.1 FLASH OPTION BYTES

The option bytes allow the hardware configuration

of the microcontroller to be selected. They have no

address in the memory map and can be accessed

only in programming mode (for example using a

standard ST7 programming tool). The default con-

tent of the FLASH is fixed to FFh. To program the

FLASH devices directly using ICP, FLASH devices

are shipped to customers with the internal RC

clock source enabled. In masked ROM devices,

the option bytes are fixed in hardware by the ROM

code (see option list).

OPTION BYTE 0

OPT7= WDG HALT Watchdog and HALT mode

This option bit determines if a RESET is generated

when entering HALT mode while the Watchdog is

active.

0: No Reset generation when entering Halt mode

1: Reset generation when entering Halt mode

OPT6= WDG SW Hardware or software watchdog

This option bit selects the watchdog type.

0: Hardware (watchdog always enabled)

1: Software (watchdog to be enabled by software)

OPT5 = CSS Clock security system on/off

This option bit enables or disables the clock secu-

rity system function (CSS) which includes the

clock filter and the backup safe oscillator.

0: CSS enabled

1: CSS disabled

OPT4:3= VD[1:0] Voltage detection

These option bits enable the voltage detection

block (LVD, and AVD) with a selected threshold for

the LVD and AVD (EVD+AVD).

Caution: If the medium or low thresholds are se-

lected, the detection may occur outside the speci-

fied operating voltage range. Below 3.8V, device

operation is not guaranteed. For details on the

AVD and LVD threshold levels refer to section

12.3.2 on page 145

OPT2 = Reserved, must be kept at default value.

OPT1= PKG0 Package selection bit 0

This option bit is not used.

STATIC OPTION BYTE 0

STATIC OPTION BYTE

170

WDG

OSCTYPE

OSCRANGE

Default

Selected Low Voltage Detector

VD1

VD0

LVD and AVD Off

Lowest Threshold: (VDD~3V)

Med. Threshold (VDD~3.5V)

Highest Threshold (VDD~4V)

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